hexagon: add f32 ssm_conv op#20122
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max-krasnyansky merged 6 commits intoggml-org:masterfrom Mar 6, 2026
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Nice!
We can improve DMA pipelining and precompute more per-thread state in a local context. Ok to do that in a followup though.
test-backend-ops is passing on S25 and Gen5, but failing on S24 (gen3, hex-arch v75).
[SSM_CONV] ERR = 0.045690326 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,1024,1,1],ne_b=[3,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.027886839 > 0.000000100 SSM_CONV(type=f32,ne_a=[6,1024,1,1],ne_b=[3,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.069031246 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,1024,4,1],ne_b=[3,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.011857102 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,1536,1,1],ne_b=[3,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.021944322 > 0.000000100 SSM_CONV(type=f32,ne_a=[6,1536,1,1],ne_b=[3,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.046434721 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,1536,4,1],ne_b=[3,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.009548537 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,2048,1,1],ne_b=[3,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.023424253 > 0.000000100 SSM_CONV(type=f32,ne_a=[6,2048,1,1],ne_b=[3,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.022690631 > 0.000000100 SSM_CONV(type=f32,ne_a=[3,2048,4,1],ne_b=[3,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.020098070 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,1024,1,1],ne_b=[4,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.033635444 > 0.000000100 SSM_CONV(type=f32,ne_a=[8,1024,1,1],ne_b=[4,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.053863172 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.046260286 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.019073288 > 0.000000100 SSM_CONV(type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.019367290 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.003745381 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.017238832 > 0.000000100 SSM_CONV(type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.015438665 > 0.000000100 SSM_CONV(type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.026768994 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,1024,1,1],ne_b=[9,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.013978035 > 0.000000100 SSM_CONV(type=f32,ne_a=[18,1024,1,1],ne_b=[9,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.020436464 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,1024,4,1],ne_b=[9,1024,1,1]): FAIL
[SSM_CONV] ERR = 0.003860245 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,1536,1,1],ne_b=[9,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.006388827 > 0.000000100 SSM_CONV(type=f32,ne_a=[18,1536,1,1],ne_b=[9,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.021140220 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,1536,4,1],ne_b=[9,1536,1,1]): FAIL
[SSM_CONV] ERR = 0.005109369 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,2048,1,1],ne_b=[9,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.006309449 > 0.000000100 SSM_CONV(type=f32,ne_a=[18,2048,1,1],ne_b=[9,2048,1,1]): FAIL
[SSM_CONV] ERR = 0.011532749 > 0.000000100 SSM_CONV(type=f32,ne_a=[9,2048,4,1],ne_b=[9,2048,1,1]): FAIL
I'll dig some more tomorrow to see what's up with that.
The error is quite large. LFM2 output seems OK but it would be good to fix those errors.
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Latest updates fixed all test-backend-ops failures on Snapdragon Gen3,4,5 and X-Elites. |
bartowski1182
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Mar 10, 2026
* hexagon: add ssm_conv op * hexagon: hvx kernel is functional * hexagon: improvements to ssm-conv hvx kernel * hexagon: added dma to ssm-conv hvx kernel * hexagon: ssm-conv dynamically compute gather scratchpad * hex-ssm-conv: add local context and fix various issues (spad indexing, etc) --------- Co-authored-by: Max Krasnyansky <maxk@qti.qualcomm.com>
Ethan-a2
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Mar 20, 2026
* hexagon: add ssm_conv op * hexagon: hvx kernel is functional * hexagon: improvements to ssm-conv hvx kernel * hexagon: added dma to ssm-conv hvx kernel * hexagon: ssm-conv dynamically compute gather scratchpad * hex-ssm-conv: add local context and fix various issues (spad indexing, etc) --------- Co-authored-by: Max Krasnyansky <maxk@qti.qualcomm.com>
Seunghhon
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Apr 26, 2026
* hexagon: add ssm_conv op * hexagon: hvx kernel is functional * hexagon: improvements to ssm-conv hvx kernel * hexagon: added dma to ssm-conv hvx kernel * hexagon: ssm-conv dynamically compute gather scratchpad * hex-ssm-conv: add local context and fix various issues (spad indexing, etc) --------- Co-authored-by: Max Krasnyansky <maxk@qti.qualcomm.com>
rsenthilkumar6
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May 1, 2026
* hexagon: add ssm_conv op * hexagon: hvx kernel is functional * hexagon: improvements to ssm-conv hvx kernel * hexagon: added dma to ssm-conv hvx kernel * hexagon: ssm-conv dynamically compute gather scratchpad * hex-ssm-conv: add local context and fix various issues (spad indexing, etc) --------- Co-authored-by: Max Krasnyansky <maxk@qti.qualcomm.com>
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