Add support for stage-2 page tables by m4tx · Pull Request #94 · google/aarch64-paging

m4tx · 2025-11-28T15:27:33Z

No description provided.

m4tx · 2026-01-15T15:18:03Z

@qwandor this still needs more polishing and testing, but may I ask to have a look when you have some free time to verify whether the overall approach and structure is something sensible for aarch64-paging? I don't ask for a full review yet; I just want to see whether it's worth finishing this, or is there any other way to implement this that we'd want to use.

qwandor

This seems like a broadly reasonable approach to me.

src/descriptor.rs

qwandor · 2026-01-23T18:24:45Z

src/lib.rs

        translation: T,
        asid: usize,
        rootlevel: usize,
        translation_regime: TranslationRegime,


This makes it possible to construct a Mapping with a TranslationRegime which doesn't match the attributes type. We should prevent that somehow. Maybe there could be separate types for Stage1TranslationRegime and Stage2TranslationRegime, and they could specify the corresponding attributes type via an associated type?

That's true - this is a pretty big refactor though, would it make sense to combine it with splitting the Stage 1 attributes into different types and making it a separate PR? I've got an initial version here: m4tx/aarch64-paging@stage-2...m4tx:aarch64-paging:attribute-refactor

That looks reasonable, I'll review it separately once you send a PR for it.

qwandor · 2026-01-23T18:31:38Z

src/paging.rs

    El2And0,
    /// Non-secure EL1&0, stage 1.
    El1And0,
+    /// Non-secure Stage 2.


This applies to the other existing options too, but does secure world actually use different translation regimes to normal world?

qwandor · 2026-01-23T18:34:31Z

src/descriptor.rs

+    /// Attribute bits for a mapping in a Stage 1 page table.
    #[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
-    pub struct Attributes: usize {
+    pub struct Stage1Attributes: usize {


Possibly we should split this into two different types, as some of the existing translation regimes have slightly different attribute bits too.

See the comment above, I've got an initial version of this here: m4tx/aarch64-paging@stage-2...m4tx:aarch64-paging:attribute-refactor

Thanks, that looks reasonable, I'll review it properly once this is merged.

src/descriptor.rs

qwandor · 2026-02-16T22:54:26Z

src/descriptor.rs

+        const TABLE_OR_PAGE = 1 << 1;
+
+        const MEMATTR_DEVICE_nGnRnE = 0 << 2;
+        const MEMATTR_NORMAL        = 0xf << 2; // Example value


What do you mean by this being an "example value"?

Sorry, left it after prototyping quickly - I've replaced this with proper attributes now.

qwandor · 2026-02-16T22:55:36Z

src/descriptor.rs


    const PHYSICAL_ADDRESS_BITMASK: usize = !(PAGE_SIZE - 1) & !(0xffff << 48);

+    pub(crate) fn new(value: usize) -> Self {


Can this be const? Then you can use it for EMPTY too.

Good point - indeed, it can.

qwandor

This looks good to me. @ardbiesheuvel, do you want to have a look at it before we merge it?

ardbiesheuvel · 2026-02-23T17:03:45Z

This looks good to me. @ardbiesheuvel, do you want to have a look at it before we merge it?

Please squash these changes together so I can look at the end result, rather than the journey that brought us there :-)

(Multiple patches in a PR is fine, and even preferred, if they consist of logical discrete steps implementing the goal of the PR. Incremental changes in response to review feedback should be squashed together).

Thanks.

m4tx · 2026-02-23T17:32:41Z

@ardbiesheuvel sure, there you go!

ardbiesheuvel · 2026-02-23T17:46:59Z

src/descriptor.rs

+        if (old_bits ^ new_bits) & (MEM_ATTR_MASK | SH_MASK) != 0 {
+            return false;
+        }
+        true


Does this permit turning a block mapping into a table mapping? That is a problem, because it not only violates BBM, it also corrupts our data structures.

Ah, that's a very fair point. I've changed this code to be written in an allowlist-style, similarly to the Stage1 implementation, so that even with new attributes potentially being added, it will still be safe.

ardbiesheuvel · 2026-02-24T18:58:45Z

src/descriptor.rs

-        if !old.contains(Self::VALID) || !new.contains(Self::VALID) {
-            return true;
-        }
-


Are you removing this because it is redundant? That's fine, but please do it in a separate patch.

ardbiesheuvel · 2026-02-24T18:59:52Z

src/descriptor.rs

-            return false;
-        }
-        true
+        (!old & new & !allowed_mask).is_empty() && (old & !new & !allowed_mask).is_empty()


This could be ((old ^ new) & !allowed_mask).is_empty(), right?

qwandor marked this pull request as ready for review December 5, 2025 13:02

qwandor marked this pull request as draft December 5, 2025 13:02

qwandor added the enhancement New feature or request label Dec 5, 2025

m4tx force-pushed the stage-2 branch 5 times, most recently from 74bc800 to 6e28cde Compare January 15, 2026 15:16

m4tx marked this pull request as ready for review January 15, 2026 15:16

qwandor reviewed Jan 23, 2026

View reviewed changes

m4tx requested a review from qwandor February 16, 2026 15:15

qwandor reviewed Feb 16, 2026

View reviewed changes

qwandor requested a review from ardbiesheuvel February 16, 2026 22:57

qwandor approved these changes Feb 22, 2026

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Add support for stage-2 page tables

abf1760

m4tx force-pushed the stage-2 branch from 7c788ce to abf1760 Compare February 23, 2026 17:32

ardbiesheuvel reviewed Feb 23, 2026

View reviewed changes

address review comments

fdd0b7c

m4tx requested a review from ardbiesheuvel February 24, 2026 12:07

ardbiesheuvel reviewed Feb 24, 2026

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		const PHYSICAL_ADDRESS_BITMASK: usize = !(PAGE_SIZE - 1) & !(0xffff << 48);

		pub(crate) fn new(value: usize) -> Self {

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m4tx commented Nov 28, 2025

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ardbiesheuvel commented Feb 23, 2026

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m4tx commented Jan 15, 2026 •

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