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ZSTD decoder: cocotb utils and decoder testcases, verilog helper modules#3035

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rw1nkler wants to merge 31 commits intogoogle:mainfrom
antmicro:zstd_dec_verilog
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ZSTD decoder: cocotb utils and decoder testcases, verilog helper modules#3035
rw1nkler wants to merge 31 commits intogoogle:mainfrom
antmicro:zstd_dec_verilog

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@rw1nkler rw1nkler commented Sep 10, 2025 •
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Added functionality:

  • multiple testcases covering the decoding of frames with "compressed" blocks of different type
  • cocotb testing utilities for common operations on XLS channels
  • collection of PnR benchmarks
  • ZSTD frame generator
  • tests of axi ram writer/reader procs as well as memreader & memwriter

Supersedes #2717

@rw1nkler rw1nkler mentioned this pull request Sep 10, 2025
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@dplassgit dplassgit requested a review from proppy September 10, 2025 18:55
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rw1nkler commented Sep 16, 2025

@proppy Please let us know if there’s anything else we can do to move this forward

proppy
proppy reviewed Sep 16, 2025
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Comment thread dependency_support/com_github_alexforencich_verilog_axi/BUILD.bazel
@@ -0,0 +1,15 @@
# Copyright 2025 The XLS Authors
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@proppy proppy Sep 16, 2025

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I don't think there is a precedent for our project to import SystemVerilog third_party dependency, I'll have to figure out how to make this work.

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as we discussed, it might be worth exploring landing the verilog dependency in a separate PR (and merge first the cocotb tests that don't depend on it)

rw1nkler and others added 26 commits September 19, 2025 15:38
@rw1nkler
Add a separate test case for each test file
2dca4ce 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@sgizler @rw1nkler
Add "pytype binary, library" hint
53571ca
@koblonczek @rw1nkler
Add cocotb tests
af3b51a 
Add cocotb testing utilities:
- XLSStruct for easier handling and serializing/deserializing XLS structs
- XLSChannel that serves as a dummy receiving channel
- XLSMonitor that monitors transactions on an XLS channel
- XLSDriver that can send data on an XLS channel
- LatencyScoreboard that can measure latency between corresponding transactions on input and output buses
- File-backed AXI memory python model

Add cocotb tests for:
- modules/zstd/memory/MemReader
- modules/zstd/memory/AxiWriter
- modules/zstd/memory/MemWriter

Co-authred-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Co-authred-by: Robert Winkler <rwinkler@antmicro.com>
Co-authred-by: Michal Czyz <mczyz@antmicro.com>
Signed-off-by: Michal Czyz <mczyz@antmicro.com>
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Krzysztof Obłonczek <koblonczek@antmicro.com>
@lpawelcz @rw1nkler
xls/modules/zstd: expose fifo verilog module
11a248d 
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/cocotb: Add ZSTD frame generator library
e0856b5 
This reverts commit 04ad379225b706ddf492d440c673e77348d7a409.
@lpawelcz @rw1nkler
dependency_support: Add zstandard python library
a0a309f 
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd: Add verilog simulation of the ZstdDecoder
bffd3a3 
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@koblonczek @rw1nkler
Use frame generator in tests
de73006 
Co-authored-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Krzysztof Obłonczek <koblonczek@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/zstd_dec: Write decoded data to the memory
5b6d804 
ZstdDecoder:
  * Cocotb tests:
    * Move third-party verilog modules (AXI Interconnect) to external directory
    * Replace AXI Interconnect with AXI Crossbar that handles simultaneous AXI Read
      and Write transactions
    * Add reference memory and fill it with expected data for comparison
      against testbench memory at the end of the decoding

Internal-tag: [#67272]
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/zstd_dec: Remove stream-based output interface
03aef2a 
Adjust cocotb test to:
* Removal of Repacketizer proc
* Removal of stream-based output channels from
  * SequenceExecutor
  * ZstdDecoder

Internal-tag: [#67272]
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/zstd_dec_cocotb_test: Improve Verilog simulation
9adb781 
* Decode multiple ZSTD frames in a single cocotb testbench
* Add one cocotb testbench per type of the ZSTD frames:
  * Frames with RAW blocks only
  * Frames with RLE blocks only
  * Frames with Compressed blocks only (disabled)
  * Frames with mixed blocks (disabled)

Internal-tag: [#67272]
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/memory/mem_writer: Reduce the amount of random test cases
eaeb6ed 
Caused by timeouts after rebase - looks like regression in the
performance of codegen

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd/memory: Move verilog sources to rtl subdirectory
fa09c1f 
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
xls/modules/zstd/external: Add docstring and license for third party …
e3e64bd 
…sources

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@lpawelcz @rw1nkler
modules/zstd: Adjust cocotb test to removal of RESET CSR
bcaf1c5 
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
@wsipak @lpawelcz @rw1nkler
Style changes
7153a6a 
Improve formatting, wording and fix lint issues

Co-authored-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
@rw1nkler
Extend cocotb tests of ZSTD decoder
aa24e64 
Co-authored-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Co-authored-by: Krzysztof Oblonczek <koblonczek@antmicro.com>
Co-authored-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Dominik Lau <dlau@antmicro.com>
Co-authored-by: Szymon Gizler <sgizler@antmicro.com>

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Collect P&R benchmarks
be24b01 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Add fixed version of RamDemux together with a test
5e90234 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@sgizler @rw1nkler
Document decoder testing
49116aa
@rw1nkler
dependency_support: Add verilog_axi package
8cc9a8e 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Use bazel package with verilog_axi
e27ac0b 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Downgrade dependencies
3392904 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Run tests selectively in GitHub CI
e860acf 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Remove zstandard python library
978cb54 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
modules: zstd: update readme
aac3756 
Co-autored-by: Dominik Lau <dlau@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Add cocotb check for verifying huffman codes
a914314 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
modules: zstd: cocotb: drop unused testcase
1a5df3b 
Co-autored-by: Dominik Lau <dlau@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
modules: zstd: disable huffman code builder PnR
0393f5b 
Co-autored-by: Dominik Lau <dlau@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
modules: zstd: fix formatting
86d2c87 
Co-autored-by: Dominik Lau <dlau@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
@rw1nkler
Update python lock file
acf0ffd 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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proppy commented Oct 10, 2025

Marking this as draft until it's ready to review again.

@proppy proppy marked this pull request as draft October 10, 2025 05:50
@magancarz magancarz mentioned this pull request Dec 31, 2025
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rw1nkler commented Jan 2, 2026

Superseded by #3636

@rw1nkler rw1nkler closed this Jan 2, 2026
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@rw1nkler @proppy @sgizler @koblonczek @lpawelcz @wsipak