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MSI-X support #2101
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MSI-X support #2101
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@@ -36,6 +36,8 @@ impl VirtioNetDriver<Uninit> { | |
| notif_cfg, | ||
| isr_cfg, | ||
| dev_cfg_list, | ||
| #[cfg(all(feature = "pci", target_arch = "x86_64"))] | ||
| msix_table, | ||
| .. | ||
| } = caps_coll; | ||
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@@ -44,14 +46,21 @@ impl VirtioNetDriver<Uninit> { | |
| return Err(error::VirtioNetError::NoDevCfg(device_id)); | ||
| }; | ||
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| let irq = device.get_irq(); | ||
| if irq.is_none() { | ||
| warn!("No interrupt lanes found for virtio-net."); | ||
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Member
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Should this not be an error instead?
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. According to the section 7.5.1.1.13 of the PCIe specification version 6.0, "A [Interrupt Pin Register] value of 00h indicates that the Function uses no legacy interrupt Message(s)," so a device may be well-behaving and still not have an interrupt pin and line, in which case we may still be able to use MSI-X. There are reserved and unknown values and values that indicate no connection to the interrupt controller but for |
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| } | ||
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| Ok(VirtioNetDriver { | ||
| dev_cfg, | ||
| com_cfg, | ||
| isr_stat: isr_cfg, | ||
| notif_cfg, | ||
| #[cfg(all(feature = "pci", target_arch = "x86_64"))] | ||
| msix_table, | ||
| inner: Uninit, | ||
| num_vqs: 0, | ||
| irq: device.get_irq().unwrap(), | ||
| irq, | ||
| checksums: ChecksumCapabilities::default(), | ||
| }) | ||
| } | ||
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@@ -537,6 +537,38 @@ pub(crate) fn init() { | |
| }); | ||
| } | ||
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| /// MSI-X Table entry. | ||
| #[repr(C)] | ||
| pub(crate) struct MsixTableEntry { | ||
| /// Message Address | ||
| message_address: u32, | ||
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| /// Message Upper Address | ||
| message_upper_address: u32, | ||
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| /// Message Data | ||
| message_data: u32, | ||
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| /// Vector Control | ||
| vector_control: u32, | ||
| } | ||
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Member
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Would it make sense to upstream this to That crate currently does not use any volatile operations at all, though. Is volatile necessary here? Should |
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| impl MsixEntry { | ||
| #[cfg(target_arch = "x86_64")] | ||
| pub fn configure(msix_entry: volatile::VolatilePtr<'_, Self>, vector: u8) { | ||
| use bit_field::BitField; | ||
| use volatile::map_field; | ||
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| // Mask the entry because "[s]oftware must not modify the Address, Data, or Steering Tag fields | ||
| // of an entry while it is unmasked." (PCIe spec. 6.1.4.2) | ||
| map_field!(msix_entry.control).update(|mut control| *control.set_bit(0, true)); | ||
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| map_field!(msix_entry.addr_low).update(|mut addr_low| *addr_low.set_bits(20..32, 0xfee)); | ||
| map_field!(msix_entry.data).update(|mut data| *data.set_bits(0..8, u32::from(vector) + 32)); | ||
| map_field!(msix_entry.control).update(|mut control| *control.set_bit(0, false)); | ||
| } | ||
| } | ||
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| /// A module containing PCI specific errors | ||
| /// | ||
| /// Errors include... | ||
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