Incorrect decoding of IM 0 with 0xE9 - JP (HL) - during Int Act #3
Description
dmb@quadhog:~/atom/Z80Decoder$ ./decodez80 -d0 -ahiy -s2 ../perfect6502/otir.bin
WARNING: Incorrect cycle type for prefix/opcode: NONE
WARNING: Incorrect cycle type for prefix/opcode: MEMRD
???? : 00 : NOP : 19/ 0 : A=?? F=???????? BC=???? DE=???? HL=???? IX=???? IY=???? SP=???? : WZ=???? IR=???? IFF=?? IM=?
???? : 00 : NOP : 4/ 0 : A=?? F=???????? BC=???? DE=???? HL=???? IX=???? IY=???? SP=???? : WZ=???? IR=???? IFF=?? IM=?
???? : C3 04 00 : JP 0004h : 10/ 0 : A=?? F=???????? BC=???? DE=???? HL=???? IX=???? IY=???? SP=???? : WZ=0004 IR=???? IFF=?? IM=?
0004 : ED 46 : IM 0 : 8/ 0 : A=?? F=???????? BC=???? DE=???? HL=???? IX=???? IY=???? SP=???? : WZ=0004 IR=???? IFF=?? IM=0
0006 : FB : EI : 4/ 0 : A=?? F=???????? BC=???? DE=???? HL=???? IX=???? IY=???? SP=???? : WZ=0004 IR=???? IFF=11 IM=0
0007 : 21 20 00 : LD HL,0020h : 10/ 0 : A=?? F=???????? BC=???? DE=???? HL=0020 IX=???? IY=???? SP=???? : WZ=0004 IR=???? IFF=11 IM=0
000A : 01 01 FF : LD BC,FF01h : 10/ 0 : A=?? F=???????? BC=FF01 DE=???? HL=0020 IX=???? IY=???? SP=???? : WZ=0004 IR=???? IFF=11 IM=0
000D : ED B3 : OTIR : 23/ 0 : A=?? F=S V BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
WARNING: Incorrect cycle type for write op1: FETCH
000D : CB 46 : BIT 0,(HL) : 16/ 0 : A=?? F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
000F : 00 : NOP : 4/ 0 : A=?? F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0010 : F5 : PUSH AF : 11/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0011 : 00 : NOP : 4/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0012 : 00 : NOP : 4/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0013 : 76 : HALT : 4/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0014 : : NOP : 4/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
0014 : : NOP : 4/ 0 : A=55 F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
The problem is all INT interrupts are handled by a z80_interrupt_int() virtual instruction, and this expects two write cycle (pushing the PC to stack). This doesn't happen in the above test case, because a JP (HL) is placed on the bus during the Int Act Cycle:
M1 FETCH 0 0 1 0 1 1 1 0 ff
M1 FETCH 0 0 1 0 1 1 1 1 ed
M1 FETCH 0 0 1 0 1 1 1 0 ed
M1 NONE 1 1 1 1 1 1 1 1 ed
M1 NONE 1 1 1 0 1 1 1 0 ed
M1 NONE 1 1 1 0 1 1 1 1 ed
M1 NONE 1 1 1 1 1 1 1 0 ed
M1 NONE 0 1 1 1 1 1 1 1 ed
M1 FETCH 0 0 1 0 1 1 1 0 ed
M1 FETCH 0 0 1 0 1 1 1 1 b3
M1 FETCH 0 0 1 0 1 1 1 0 b3
M1 NONE 1 1 1 1 1 1 1 1 b3
M1 NONE 1 1 1 0 1 1 1 0 b3
M1 NONE 1 1 1 0 1 1 1 1 b3
M1 NONE 1 1 1 1 1 1 1 0 b3
M1 NONE 1 1 1 1 1 1 1 1 b3
M1 NONE 1 1 1 1 1 1 1 0 b3
M1 NONE 1 1 1 1 1 1 1 1 b3
M2 MEMRD 1 0 1 0 1 1 1 0 b3
M2 MEMRD 1 0 1 0 1 1 1 1 00
M2 MEMRD 1 0 1 0 1 1 1 0 00
M2 MEMRD 1 0 1 0 1 1 1 1 00
M2 NONE 1 1 1 1 1 1 1 0 00
M2 NONE 1 1 1 1 1 1 1 1 00
M2 NONE 1 1 1 1 1 1 1 0 00 : Rd=00
M3 IOWR 1 1 0 1 0 1 1 1 00
M3 IOWR 1 1 0 1 0 1 1 0 00
M3 IOWR 1 1 0 1 0 1 1 1 00
M3 IOWR 1 1 0 1 0 1 1 0 00
M3 IOWR 1 1 0 1 0 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 1 1 1 1 1 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 1 1 1 1 1 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 1 1 1 1 1 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 1 1 1 1 1 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 1 1 1 1 1 1 1 1 00
M3 NONE 1 1 1 1 1 1 1 0 00
M3 NONE 0 1 1 1 1 1 1 1 00
M3 NONE 0 1 1 1 1 1 1 0 00
M3 NONE 0 1 1 1 1 1 1 1 00
M3 NONE 0 1 1 1 1 1 1 0 00
M3 NONE 0 1 1 1 1 1 1 1 00 : Wr=00
000D : ED B3 : OTIR : 23/ 0 : A=?? F=S V BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
M4 INTACK 0 1 1 1 0 1 1 0 00
M4 INTACK 0 1 1 1 0 1 1 1 e9
M4 INTACK 0 1 1 1 0 1 1 0 e9
M4 NONE 1 1 1 1 1 1 1 1 e9
M4 NONE 1 1 1 0 1 1 1 0 e9
M4 NONE 1 1 1 0 1 1 1 1 e9
M4 NONE 1 1 1 1 1 1 1 0 e9
M4 NONE 0 1 1 1 1 1 1 1 e9
WARNING: Incorrect cycle type for write op1: FETCH
M1 FETCH 0 0 1 0 1 1 1 0 e9
M1 FETCH 0 0 1 0 1 1 1 1 cb
M1 FETCH 0 0 1 0 1 1 1 0 cb
M1 NONE 1 1 1 1 1 1 1 1 cb
M1 NONE 1 1 1 0 1 1 1 0 cb
M1 NONE 1 1 1 0 1 1 1 1 cb
M1 NONE 1 1 1 1 1 1 1 0 cb
M1 NONE 0 1 1 1 1 1 1 1 cb
M1 FETCH 0 0 1 0 1 1 1 0 cb
M1 FETCH 0 0 1 0 1 1 1 1 46
M1 FETCH 0 0 1 0 1 1 1 0 46
M1 NONE 1 1 1 1 1 1 1 1 46
M1 NONE 1 1 1 0 1 1 1 0 46
M1 NONE 1 1 1 0 1 1 1 1 46
M1 NONE 1 1 1 1 1 1 1 0 46
M1 NONE 1 1 1 1 1 1 1 1 46
M2 MEMRD 1 0 1 0 1 1 1 0 46
M2 MEMRD 1 0 1 0 1 1 1 1 cb
M2 MEMRD 1 0 1 0 1 1 1 0 cb
M2 MEMRD 1 0 1 0 1 1 1 1 cb
M2 NONE 1 1 1 1 1 1 1 0 cb
M2 NONE 1 1 1 1 1 1 1 1 cb
M2 NONE 1 1 1 1 1 1 1 0 cb
M2 NONE 0 1 1 1 1 1 1 1 cb : Rd=CB
000D : CB 46 : BIT 0,(HL) : 16/ 0 : A=?? F= H BC=FE01 DE=???? HL=0021 IX=???? IY=???? SP=???? : WZ=000E IR=???? IFF=11 IM=0
The interrupt handling needs refactoring to better deal with this case.
Probably when INTACK is detected, the IFF flags should be immedietly opdated, and a interrupt should be logged.
The IM0 can be handled as a normal instruction, and only IM1 and IM2 handled as virtual instructions.