C++ Software Engineer · Ultra Low-Latency · HFT Infrastructure

I engineer ultra low-latency trading systems in C++20/23 on Linux.
Every design decision is driven by one constraint: latency.
No exceptions. No virtual dispatch. No heap allocation in the critical path.

Currently building an open-source Ultra Low-Latency Trading System in C++20 on Linux —
designed for nanosecond-critical execution with fault-tolerant distributed state.

• Lock-free concurrency — SPSC/MPMC queues, ABA prevention via tagged pointers, epoch-based and hazard pointer reclamation
• CPU-level optimization — cache-line aware data layout, SIMD/AVX vectorization, branch prediction control, prefetching
• Kernel bypass — DPDK, RDMA, onload/ef_vi for sub-microsecond network I/O
• Memory discipline — pool allocators, slab allocation, zero dynamic allocation in hot path, NUMA-aware design
• Performance engineering — perf, Valgrind, flamegraphs, hardware PMU counters, L1/L2/LLC miss analysis

Acceleration of Parallel SAT Solver for Cryptanalysis of Hash Functions
Co-author · NSU Cryptography Summer School-Conference 2025 · pp. 132-142

Up to 41% runtime reduction on multi-threaded configurations via low-level algorithmic optimization.

WorldSkills — 2nd place, Neural Interface Design (2026)

Kernel bypass networking · FPGA-accelerated execution · RDMA · DPDK · Infiniband · Busy-polling networking · CPU pinning & IRQ affinity · Huge pages & TLB optimization · PTP/IEEE 1588 time synchronization · Lock-free memory reclamation · CPU microarchitecture optimization

English — fluent. Open to relocation globally.