CSN-221 Course Project-2: Implementation of Configurable Cache

Table of Contents

1. About The Project
2. Getting Started
   • EDA Playground
     • Login
     • Code
     • Simulator Setup
     • Run Code
3. Contributors

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About The Project

This is a simulation of a configurable cache in SystemVerilog. In this simulation, we take instructions as input. (Since EDA playground has file size limit of 1,00,000 characters, we have considered at most 10,000 instructions.) It has following format:

• Blank space followed by operation bit (1 for read and 2 for write)
• Memory address of 6 hex-digits.

The address tag is compared to the tag value in the cache and , the data is either found in the cache, identifying a hit, or in case of a miss, it's pulled from the memory. Thereafter, based on the type of operation, read or write takes place. Finally hit rate is calculated and displayed along with number of read/write hits.

This is our submission for CSN-221 Course Project-1.

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Getting Started

Since there is no satisfactory compiler for SystemVerilog, so this Project has had to be run on online SystemVerilog Simulators like Aldec Riviera Pro 2022.04, which we used to make this project.

To run this project follow these steps:

EDA Playground

This is a web application that allows users to edit, simulate, synthesize, and share their HDL code written in languages like SystemVerilog.

Login

• Go to https://www.edaplayground.com/
• Login by clicking on Login in the top-right corner

Code

• Copy-paste the code in testbench.sv into testbench.sv on EDA-Playground
• Create a new file named Assembler.sv and paste the Assembler.sv code into it.
• From http://www.cs.toronto.edu/~reid/csc150/02f/a2/traces.html copy the instruction sets and paste them into input.txt. If _Number_instructions is greater than 10,000, take first 10,000 instructions only.
• Change _Number_instructions from line number 8 of testbench.sv and line number 1 from Assembler.sv accordingly.
• If chosen instruction set is qsort or mm16, then change line[2] to line[1] from line number 80 of Assembler.sv.
• Set up the configurations by making necessary changes in line number 4 to 8 in testbench.sv.
• By default, input.txt contains instruction set lu and configuration is set as 32 kB cache size, 8 ways and block size of 64 bytes.

Simulator setup

• Click on Tools & Simulators in left side-bar
• Select Aldec Riviera Pro 2022.04 from the dropdown menu

Run code

• Save the playground and then click Run
• Output will be shown in Log tab at the bottom

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Contributors

Contributors of this Group project:

Ashutosh Kalidas Pise (21114073)

Ashutosh Kumar (21114021)

KirtanKumar VijayKumar Patel (21114051)

Mudit Gupta (21114061)

Rishi Kejriwal (21114081)

Rohan Kalra (21114083)