fix: correctly parse multiple cache instances via sysfs#64
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dadealus wants to merge 1 commit intolevel1techs:mainfrom
Open
fix: correctly parse multiple cache instances via sysfs#64dadealus wants to merge 1 commit intolevel1techs:mainfrom
dadealus wants to merge 1 commit intolevel1techs:mainfrom
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The raw_cpuid parser only queried the core it was running on, leading to incorrect topology maps on asymmetric processors like the Ryzen 9 9950X3D where one CCD has 96MB of L3 and the other has 32MB. This implements a sysfs-based cache reader similar to lscpu that correctly aggregates the topology across all distinct cache instances.
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Summary
raw_cpuidonly queried the core it was running on, leading to incomplete L3 cache reporting on asymmetric NUMA processors (like the Ryzen 9 9950X3D)./sys/devices/system/cpu/cpu*/cache/index*) that correctly aggregates topology across all distinct cache instances.Description
While testing
siomonon an ASUS X870E ProArt motherboard with a Ryzen 9 9950X3D, we noticed that it was only detecting 96MB of L3 cache instead of the full 128MB.The original
gather_cachefunction utilized theraw_cpuidcrate, which only reads the CPU instruction data for the thread the program starts on. On a 9950X3D, if it lands on the 3D V-Cache CCD, it reports 96MB and assumes it applies across the whole CPU, completely missing the 32MB standard L3 cache on the second CCD.This PR introduces a new
gather_cache_sysfsfunction that acts similarly tolscpu. It iterates through the Linux kernel's sysfs cache directories and maps out every distinct instance using theshared_cpu_list. This correctly aggregates the total L3 cache size and identifies the distinct instances across multiple NUMA nodes.Disclaimer: This Pull Request was built with AI assistance to help diagnose the issue and formulate the sysfs parsing logic.