release/20.x: [WebAssembly] Fix inline assembly with vector types (#146574)#147409
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tstellar merged 1 commit intollvm:release/20.xfrom Jul 7, 2025
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release/20.x: [WebAssembly] Fix inline assembly with vector types (#146574)#147409tstellar merged 1 commit intollvm:release/20.xfrom
tstellar merged 1 commit intollvm:release/20.xfrom
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@sunfishcode What do you think about merging this PR to the release branch? |
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@llvm/pr-subscribers-backend-webassembly Author: None (llvmbot) ChangesBackport a8a9a7f Requested by: @sunfishcode Full diff: https://github.com/llvm/llvm-project/pull/147409.diff 2 Files Affected:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
index 17889dacc868c..31a33c1e7365b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
@@ -64,8 +64,8 @@ def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
-def V128 : WebAssemblyRegClass<[v8f16, v4f32, v2f64, v2i64, v4i32, v16i8,
- v8i16],
+def V128 : WebAssemblyRegClass<[v2i64, v4i32, v16i8, v8i16,
+ v8f16, v4f32, v2f64],
128, (add V128_0)>;
def FUNCREF : WebAssemblyRegClass<[funcref], 0, (add FUNCREF_0)>;
def EXTERNREF : WebAssemblyRegClass<[externref], 0, (add EXTERNREF_0)>;
diff --git a/llvm/test/CodeGen/WebAssembly/inline-asm.ll b/llvm/test/CodeGen/WebAssembly/inline-asm.ll
index 4462cfb7aa0c4..c378fd953a555 100644
--- a/llvm/test/CodeGen/WebAssembly/inline-asm.ll
+++ b/llvm/test/CodeGen/WebAssembly/inline-asm.ll
@@ -129,7 +129,18 @@ entry:
ret i32 %ret
}
+; CHECK-LABEL: v128_load
+; CHECK: local.get 0
+; CHECK-NEXT: v128.load 0
+; CHECK-NEXT: local.set 1
+define <4 x i32> @v128_load(ptr %v) #1 {
+entry:
+ %0 = tail call <4 x i32> asm "local.get $1\0Av128.load 0\0Alocal.set $0", "=r,r"(ptr %v)
+ ret <4 x i32> %0
+}
+
attributes #0 = { nounwind }
+attributes #1 = { "target-features"="+simd128" }
!0 = !{i32 47}
!1 = !{i32 145}
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sunfishcode
approved these changes
Jul 7, 2025
github-project-automation
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moved this from Needs Triage
to Needs Merge
in LLVM Release Status
This commit fixes using inline assembly with v128 results. Previously this failed with an internal assertion about a failure to legalize a `CopyFromReg` where the source register was typed `v8f16`. It looks like the type used for the destination register was whatever was listed first in the `def V128 : WebAssemblyRegClass` listing, so the types were shuffled around to have a default-supported type. A small test was added as well which failed to generate previously and should now pass in generation. This test passed on LLVM 18 additionally and regressed by accident in llvm#93228 which was first included in LLVM 19. (cherry picked from commit a8a9a7f)
github-project-automation
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moved this from Needs Merge
to Done
in LLVM Release Status
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@sunfishcode (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. |
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This patch fixes an internal compiler error on asm operands with 128-bit vector types. |
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Backport a8a9a7f
Requested by: @sunfishcode