[X86] Add basic test coverage for #174169 #174226

RKSimon · 2026-01-02T18:00:58Z

No description provided.

llvmbot · 2026-01-02T18:01:31Z

@llvm/pr-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

Changes

Patch is 47.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174226.diff

4 Files Affected:

(added) llvm/test/CodeGen/X86/vector-smax-range.ll (+328)
(added) llvm/test/CodeGen/X86/vector-smin-range.ll (+347)
(added) llvm/test/CodeGen/X86/vector-umax-range.ll (+292)
(added) llvm/test/CodeGen/X86/vector-umin-range.ll (+292)

diff --git a/llvm/test/CodeGen/X86/vector-smax-range.ll b/llvm/test/CodeGen/X86/vector-smax-range.ll
new file mode 100644
index 0000000000000..56b41dad5049a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-smax-range.ll
@@ -0,0 +1,328 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2    | FileCheck %s --check-prefixes=AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=knl       | FileCheck %s --check-prefixes=AVX,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512VL
+
+define <4 x i32> @smax_v4i32_as_umax_v4i8(<4 x i32> %a0, <4 x i32> %a1) nounwind {
+; SSE2-LABEL: smax_v4i32_as_umax_v4i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psrld $30, %xmm0
+; SSE2-NEXT:    psrld $29, %xmm1
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smax_v4i32_as_umax_v4i8:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    psrld $30, %xmm0
+; SSE42-NEXT:    psrld $29, %xmm1
+; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: smax_v4i32_as_umax_v4i8:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrld $30, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $29, %xmm1, %xmm1
+; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %x0 = lshr <4 x i32> %a0, splat (i32 30)
+  %x1 = lshr <4 x i32> %a1, splat (i32 29)
+  %r = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x0, <4 x i32> %x1)
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @smax_v4i32_as_smax_v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind {
+; SSE2-LABEL: smax_v4i32_as_smax_v4i16:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smax_v4i32_as_smax_v4i16:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    psrad $16, %xmm0
+; SSE42-NEXT:    psrad $16, %xmm1
+; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: smax_v4i32_as_smax_v4i16:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrad $16, %xmm0, %xmm0
+; AVX-NEXT:    vpsrad $16, %xmm1, %xmm1
+; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %x0 = ashr <4 x i32> %a0, splat (i32 16)
+  %x1 = ashr <4 x i32> %a1, splat (i32 16)
+  %r = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x0, <4 x i32> %x1)
+  ret <4 x i32> %r
+}
+
+define <2 x i64> @smax_v2i64_as_smax_v2i16(<2 x i64> %a0, <2 x i64> %a1) nounwind {
+; SSE2-LABEL: smax_v2i64_as_smax_v2i16:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    psrad $17, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    psrlq $63, %xmm1
+; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    por %xmm0, %xmm3
+; SSE2-NEXT:    pxor %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm4
+; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; SSE2-NEXT:    pcmpeqd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pand %xmm5, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pand %xmm0, %xmm2
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smax_v2i64_as_smax_v2i16:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE42-NEXT:    psrad $31, %xmm0
+; SSE42-NEXT:    psrad $17, %xmm2
+; SSE42-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE42-NEXT:    psrlq $63, %xmm1
+; SSE42-NEXT:    movdqa %xmm2, %xmm0
+; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
+; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
+; SSE42-NEXT:    movapd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX1-LABEL: smax_v2i64_as_smax_v2i16:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX1-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX1-NEXT:    vpsrad $17, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: smax_v2i64_as_smax_v2i16:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX2-NEXT:    vpsrad $17, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
+; AVX2-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
+; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT:    retq
+;
+; AVX512F-LABEL: smax_v2i64_as_smax_v2i16:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; AVX512F-NEXT:    vpsraq $49, %zmm0, %zmm0
+; AVX512F-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX512F-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: smax_v2i64_as_smax_v2i16:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vpsraq $49, %xmm0, %xmm0
+; AVX512VL-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX512VL-NEXT:    vpmaxsq %xmm1, %xmm0, %xmm0
+; AVX512VL-NEXT:    retq
+  %x0 = ashr <2 x i64> %a0, splat (i64 49)
+  %x1 = lshr <2 x i64> %a1, splat (i64 63)
+  %r = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %x0, <2 x i64> %x1)
+  ret <2 x i64> %r
+}
+
+define <2 x i64> @smax_v2i64_as_smax_v2i32(<2 x i64> %a0, <2 x i64> %a1) nounwind {
+; SSE2-LABEL: smax_v2i64_as_smax_v2i32:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    psrad $1, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    psrlq $43, %xmm1
+; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    por %xmm0, %xmm3
+; SSE2-NEXT:    pxor %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm4
+; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; SSE2-NEXT:    pcmpeqd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pand %xmm5, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pand %xmm0, %xmm2
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smax_v2i64_as_smax_v2i32:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE42-NEXT:    psrad $31, %xmm0
+; SSE42-NEXT:    psrad $1, %xmm2
+; SSE42-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE42-NEXT:    psrlq $43, %xmm1
+; SSE42-NEXT:    movdqa %xmm2, %xmm0
+; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
+; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
+; SSE42-NEXT:    movapd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX1-LABEL: smax_v2i64_as_smax_v2i32:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX1-NEXT:    vpsrlq $43, %xmm1, %xmm1
+; AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: smax_v2i64_as_smax_v2i32:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
+; AVX2-NEXT:    vpsrlq $43, %xmm1, %xmm1
+; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
+; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT:    retq
+;
+; AVX512F-LABEL: smax_v2i64_as_smax_v2i32:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; AVX512F-NEXT:    vpsraq $33, %zmm0, %zmm0
+; AVX512F-NEXT:    vpsrlq $43, %xmm1, %xmm1
+; AVX512F-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: smax_v2i64_as_smax_v2i32:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vpsraq $33, %xmm0, %xmm0
+; AVX512VL-NEXT:    vpsrlq $43, %xmm1, %xmm1
+; AVX512VL-NEXT:    vpmaxsq %xmm1, %xmm0, %xmm0
+; AVX512VL-NEXT:    retq
+  %x0 = ashr <2 x i64> %a0, splat (i64 33)
+  %x1 = lshr <2 x i64> %a1, splat (i64 43)
+  %r = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %x0, <2 x i64> %x1)
+  ret <2 x i64> %r
+}
+
+define <4 x i64> @smax_v4i64_as_smax_v4i16(<4 x i64> %a0) nounwind {
+; SSE2-LABEL: smax_v4i64_as_smax_v4i16:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    psrad $18, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm3, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    psrad $18, %xmm3
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
+; SSE2-NEXT:    pcmpgtd %xmm4, %xmm0
+; SSE2-NEXT:    pand %xmm0, %xmm3
+; SSE2-NEXT:    pxor %xmm4, %xmm0
+; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; SSE2-NEXT:    pcmpgtd %xmm4, %xmm1
+; SSE2-NEXT:    pand %xmm1, %xmm2
+; SSE2-NEXT:    pxor %xmm4, %xmm1
+; SSE2-NEXT:    por %xmm2, %xmm1
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smax_v4i64_as_smax_v4i16:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE42-NEXT:    psrad $31, %xmm1
+; SSE42-NEXT:    psrad $18, %xmm2
+; SSE42-NEXT:    pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE42-NEXT:    psrad $31, %xmm0
+; SSE42-NEXT:    psrad $18, %xmm2
+; SSE42-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE42-NEXT:    pxor %xmm2, %xmm2
+; SSE42-NEXT:    pxor %xmm3, %xmm3
+; SSE42-NEXT:    pcmpgtq %xmm0, %xmm3
+; SSE42-NEXT:    por %xmm3, %xmm0
+; SSE42-NEXT:    pcmpgtq %xmm1, %xmm2
+; SSE42-NEXT:    por %xmm2, %xmm1
+; SSE42-NEXT:    retq
+;
+; AVX1-LABEL: smax_v4i64_as_smax_v4i16:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrad $18, %xmm2, %xmm2
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
+; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX1-NEXT:    vpsrad $18, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm2, %xmm3
+; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm2, %xmm2
+; AVX1-NEXT:    vpor %xmm0, %xmm3, %xmm0
+; AVX1-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: smax_v4i64_as_smax_v4i16:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpsrad $31, %ymm0, %ymm1
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
+; AVX2-NEXT:    vpsrad $18, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm1
+; AVX2-NEXT:    vpor %ymm0, %ymm1, %ymm0
+; AVX2-NEXT:    retq
+;
+; AVX512F-LABEL: smax_v4i64_as_smax_v4i16:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512F-NEXT:    vpsraq $50, %zmm0, %zmm0
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
+; AVX512F-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: smax_v4i64_as_smax_v4i16:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vpsraq $50, %ymm0, %ymm0
+; AVX512VL-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VL-NEXT:    vpmaxsq %ymm1, %ymm0, %ymm0
+; AVX512VL-NEXT:    retq
+  %x0 = ashr <4 x i64> %a0, splat (i64 50)
+  %r = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %x0, <4 x i64> splat (i64 -1))
+  ret <4 x i64> %r
+}
+
diff --git a/llvm/test/CodeGen/X86/vector-smin-range.ll b/llvm/test/CodeGen/X86/vector-smin-range.ll
new file mode 100644
index 0000000000000..a3c58ea5b4517
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-smin-range.ll
@@ -0,0 +1,347 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2    | FileCheck %s --check-prefixes=AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=knl       | FileCheck %s --check-prefixes=AVX,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512VL
+
+define <4 x i32> @smin_v4i32_as_umin_v4i8(<4 x i32> %a0, <4 x i32> %a1) nounwind {
+; SSE2-LABEL: smin_v4i32_as_umin_v4i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psrld $30, %xmm0
+; SSE2-NEXT:    psrld $29, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smin_v4i32_as_umin_v4i8:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    psrld $30, %xmm0
+; SSE42-NEXT:    psrld $29, %xmm1
+; SSE42-NEXT:    pminsd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: smin_v4i32_as_umin_v4i8:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrld $30, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $29, %xmm1, %xmm1
+; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %x0 = lshr <4 x i32> %a0, splat (i32 30)
+  %x1 = lshr <4 x i32> %a1, splat (i32 29)
+  %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x0, <4 x i32> %x1)
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @smin_v4i32_as_smin_v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind {
+; SSE2-LABEL: smin_v4i32_as_smin_v4i16:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smin_v4i32_as_smin_v4i16:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    psrad $16, %xmm0
+; SSE42-NEXT:    psrad $16, %xmm1
+; SSE42-NEXT:    pminsd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: smin_v4i32_as_smin_v4i16:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrad $16, %xmm0, %xmm0
+; AVX-NEXT:    vpsrad $16, %xmm1, %xmm1
+; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %x0 = ashr <4 x i32> %a0, splat (i32 16)
+  %x1 = ashr <4 x i32> %a1, splat (i32 16)
+  %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x0, <4 x i32> %x1)
+  ret <4 x i32> %r
+}
+
+define <2 x i64> @smin_v2i64_as_smin_v2i16(<2 x i64> %a0, <2 x i64> %a1) nounwind {
+; SSE2-LABEL: smin_v2i64_as_smin_v2i16:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    psrad $17, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    psrlq $63, %xmm1
+; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    por %xmm0, %xmm3
+; SSE2-NEXT:    pxor %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm3, %xmm4
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; SSE2-NEXT:    pcmpeqd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pand %xmm5, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pand %xmm0, %xmm2
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smin_v2i64_as_smin_v2i16:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE42-NEXT:    psrad $31, %xmm0
+; SSE42-NEXT:    psrad $17, %xmm2
+; SSE42-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE42-NEXT:    psrlq $63, %xmm1
+; SSE42-NEXT:    movdqa %xmm1, %xmm0
+; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
+; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
+; SSE42-NEXT:    movapd %xmm1, %xmm0
+; SSE42-NEXT:    retq
+;
+; AVX1-LABEL: smin_v2i64_as_smin_v2i16:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX1-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX1-NEXT:    vpsrad $17, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
+; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: smin_v2i64_as_smin_v2i16:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm2
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX2-NEXT:    vpsrad $17, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
+; AVX2-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
+; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT:    retq
+;
+; AVX512F-LABEL: smin_v2i64_as_smin_v2i16:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; AVX512F-NEXT:    vpsraq $49, %zmm0, %zmm0
+; AVX512F-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX512F-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
+; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: smin_v2i64_as_smin_v2i16:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vpsraq $49, %xmm0, %xmm0
+; AVX512VL-NEXT:    vpsrlq $63, %xmm1, %xmm1
+; AVX512VL-NEXT:    vpminsq %xmm1, %xmm0, %xmm0
+; AVX512VL-NEXT:    retq
+  %x0 = ashr <2 x i64> %a0, splat (i64 49)
+  %x1 = lshr <2 x i64> %a1, splat (i64 63)
+  %r = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %x0, <2 x i64> %x1)
+  ret <2 x i64> %r
+}
+
+define <2 x i64> @smin_v2i64_as_smin_v2i32(<2 x i64> %a0, <2 x i64> %a1) nounwind {
+; SSE2-LABEL: smin_v2i64_as_smin_v2i32:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm0
+; SSE2-NEXT:    psrad $1, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    psrlq $43, %xmm1
+; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    por %xmm0, %xmm3
+; SSE2-NEXT:    pxor %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm3, %xmm4
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; SSE2-NEXT:    pcmpeqd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pand %xmm5, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pand %xmm0, %xmm2
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    por %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: smin_v2i6...
[truncated]

[X86] Add basic test coverage for llvm#174169

00ca938

llvmbot added the backend:X86 label Jan 2, 2026

RKSimon enabled auto-merge (squash) January 2, 2026 18:01

RKSimon merged commit 1140957 into llvm:main Jan 2, 2026
11 of 12 checks passed

RKSimon deleted the x86-pr174169-tests branch January 2, 2026 18:52

mahesh-attarde pushed a commit to mahesh-attarde/llvm-project that referenced this pull request Jan 6, 2026

[X86] Add basic test coverage for llvm#174169 (llvm#174226)

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[X86] Add basic test coverage for #174169 #174226

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