Writing SP_CLR_HALT to SP_STATUS should continue running at whatever the current PC is. As implemented, this calls rsp_pipeline_init(), which zeroes out everything in the pipeline, including rsp->pipeline.ifrd_latch.pc.
Mostly this breaks the method I've been using of setting the PC (via SP_PC_REG) and then clearing halt and break. Execution will always start at 0. (I've seen other code do the same, but they were starting at 0 anyway.)
Saving PC around the rsp_pipeline_init() fixes this.
As an aside, I don't think the pipeline should be reset if SP_STATUS_HALT wasn't already set, but I haven't tested this.
Writing SP_CLR_HALT to SP_STATUS should continue running at whatever the current PC is. As implemented, this calls rsp_pipeline_init(), which zeroes out everything in the pipeline, including
rsp->pipeline.ifrd_latch.pc.Mostly this breaks the method I've been using of setting the PC (via SP_PC_REG) and then clearing halt and break. Execution will always start at 0. (I've seen other code do the same, but they were starting at 0 anyway.)
Saving PC around the rsp_pipeline_init() fixes this.
As an aside, I don't think the pipeline should be reset if SP_STATUS_HALT wasn't already set, but I haven't tested this.