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Add ESP32-C5 support#1

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jonny190 wants to merge 2 commits intonetmindz:CORE3from
jonny190:esp32c5-support
Open

Add ESP32-C5 support#1
jonny190 wants to merge 2 commits intonetmindz:CORE3from
jonny190:esp32c5-support

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@jonny190 jonny190 commented Feb 7, 2026

Summary

  • Add ESP32-C5 to the I2S legacy driver exclusion guard in Esp32_i2s.c (C5 lacks soc/rtc_cntl_reg.h, same as other newer chips)
  • Add ESP32-C5 bit-bang support in NeoEspBitBangMethod.cpp:
    • Use standard RISC-V cycle counter CSR 0xC00 for getCycleCount() (C5 does not have the 0x7E2 performance counter CSR used by C3/C6/H2)
    • Add C5 to GPIO register struct type guards (uses .val accessor like C3/C6/H2/P4)
    • Exclude C5 from high GPIO bank (no GPIO > 31, same as C3/H2)

Context

These changes are needed for the WLED ESP32-C5 port (Aircoookie/WLED#5355), which adds experimental dual-band WiFi 6 support via the ESP32-C5.

The ESP32-C5 is RISC-V based (like C3/C6/H2) but uses the standard cycle CSR at 0xC00 instead of the Espressif-specific 0x7E2 used by other chips. Without this fix, the bit-bang method triggers an "Illegal instruction" exception at runtime.

Test plan

  • Builds successfully for ESP32-C5 target with WLED
  • Verified correct CSR (0xC00) prevents illegal instruction crash on C5 hardware
  • No impact on other ESP32 variants (C3, C6, H2, P4, S2, S3, classic ESP32)

jonny190 added a commit to jonny190/WLED that referenced this pull request Feb 7, 2026
Replace upstream NeoPixelBus with jonny190/NeoPixelBus fork (d4bbe3f)
which adds C5 to the I2S exclusion guard and fixes the bit-bang LED
output method (cycle counter CSR 0xC00, GPIO register types).

Spell out C5 lib_deps explicitly to avoid pulling both the upstream
and fork NeoPixelBus, which causes duplicate compilation errors.

Upstream PR: netmindz/NeoPixelBus#1
@netmindz netmindz changed the base branch from master to CORE3 February 8, 2026 14:35
@jonny190
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The merge conflict is because master has been restructured since this PR was branched from 2f05279. The ESP/ESP32/ subdirectories were flattened and the IDF v5 RMT file was removed. Here's what happened to each file:

PR file (old path) Status on master
src/internal/methods/ESP/ESP32/Core_2_x/Esp32_i2s.c Moved to src/internal/methods/Esp32_i2s.c
src/internal/methods/ESP/ESP32/NeoEsp32RmtXMethod.h Deleted - master only has old IDF v4 NeoEsp32RmtMethod.h
src/internal/methods/ESP/NeoEspBitBangMethod.cpp Moved to src/internal/methods/NeoEspBitBangMethod.cpp

Two of the three fixes can be trivially rebased to the new file locations:

  1. I2S guard (Esp32_i2s.c) - just add !defined(CONFIG_IDF_TARGET_ESP32C5) to the exclusion guard at the new path
  2. Bit-bang CSR + GPIO (NeoEspBitBangMethod.cpp) - same changes, new path

The RMT changes (mem_block_symbols, single-core yield) targeted NeoEsp32RmtXMethod.h which no longer exists on master. However, WLED pins NeoPixelBus to 2f05279 which does have that file, so the RMT fixes are only needed at that pin point. If WLED updates to a newer NeoPixelBus that uses a different RMT driver, the RMT changes would need to be reworked for that driver.

I'll rebase the PR and re-apply the I2S and bit-bang fixes to the new file locations. For the RMT changes I'll keep them as-is since they apply to the 2f05279 base that WLED currently uses.

… GPIO

- ESP32-C5 uses standard RISC-V cycle counter at CSR 0xC00, not the
  Espressif-specific 0x7E2 used by C3/C6/H2/P4. Using 0x7E2 causes
  an "Illegal instruction" exception at runtime.
- Add C5 to high GPIO bank exclusion (no GPIO > 31, same as C3/H2).
- Use SOC_RMT_MEM_WORDS_PER_CHANNEL (48) for mem_block_symbols on C5
  instead of hardcoded 192, which exceeds the C5's RMT memory pool
- Add vTaskDelay after rmt_transmit on single-core C5 so the TX_DONE
  ISR can complete FreeRTOS queue operations without flush timeouts
- Add error logging for RMT init failures to aid debugging
- Remove duplicate TAG declaration, fix stray backslash
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