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Replace upstream NeoPixelBus with jonny190/NeoPixelBus fork (d4bbe3f) which adds C5 to the I2S exclusion guard and fixes the bit-bang LED output method (cycle counter CSR 0xC00, GPIO register types). Spell out C5 lib_deps explicitly to avoid pulling both the upstream and fork NeoPixelBus, which causes duplicate compilation errors. Upstream PR: netmindz/NeoPixelBus#1
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The merge conflict is because master has been restructured since this PR was branched from
Two of the three fixes can be trivially rebased to the new file locations:
The RMT changes ( I'll rebase the PR and re-apply the I2S and bit-bang fixes to the new file locations. For the RMT changes I'll keep them as-is since they apply to the |
… GPIO - ESP32-C5 uses standard RISC-V cycle counter at CSR 0xC00, not the Espressif-specific 0x7E2 used by C3/C6/H2/P4. Using 0x7E2 causes an "Illegal instruction" exception at runtime. - Add C5 to high GPIO bank exclusion (no GPIO > 31, same as C3/H2).
- Use SOC_RMT_MEM_WORDS_PER_CHANNEL (48) for mem_block_symbols on C5 instead of hardcoded 192, which exceeds the C5's RMT memory pool - Add vTaskDelay after rmt_transmit on single-core C5 so the TX_DONE ISR can complete FreeRTOS queue operations without flush timeouts - Add error logging for RMT init failures to aid debugging - Remove duplicate TAG declaration, fix stray backslash
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Summary
Esp32_i2s.c(C5 lackssoc/rtc_cntl_reg.h, same as other newer chips)NeoEspBitBangMethod.cpp:0xC00forgetCycleCount()(C5 does not have the0x7E2performance counter CSR used by C3/C6/H2).valaccessor like C3/C6/H2/P4)Context
These changes are needed for the WLED ESP32-C5 port (Aircoookie/WLED#5355), which adds experimental dual-band WiFi 6 support via the ESP32-C5.
The ESP32-C5 is RISC-V based (like C3/C6/H2) but uses the standard
cycleCSR at0xC00instead of the Espressif-specific0x7E2used by other chips. Without this fix, the bit-bang method triggers an "Illegal instruction" exception at runtime.Test plan
0xC00) prevents illegal instruction crash on C5 hardware