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    • A docker image hosting the RISC-V GNU toolchain, as well as Spike, PK, and the usual host of open-source ASIC tools. (see IIC-OSIC-TOOLS Docker Container for a complete list)
      Verilog
      0000Updated Dec 24, 2025Dec 24, 2025
    • carp-core

      Public
      The CARP Core is a 32-bit RV32IMAC_Zicsr_Zifencei_Zicntr microprocessor implementation
      SystemVerilog
      16101Updated Dec 23, 2025Dec 23, 2025
    • Website for the RAMP framework
      Python
      0000Updated Nov 15, 2025Nov 15, 2025
    • This is a containerized environment containing OSS CAD Suite and the RISC-V Toolchain, used for developing CARP IP.
      Shell
      3000Updated Sep 29, 2025Sep 29, 2025
    • carp_pcb

      Public
      C
      54000Updated Jun 13, 2025Jun 13, 2025
    • .github

      Public
      0000Updated May 17, 2024May 17, 2024
    • SourcePawn
      15000Updated Feb 18, 2024Feb 18, 2024
    • Python
      14000Updated Feb 17, 2024Feb 17, 2024
    • BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      111000Updated Feb 17, 2024Feb 17, 2024
    • tapeout-ci-2311

      Public template
      caravel-user repository for November 6, 2023 tapeout
      Verilog
      1130Updated Feb 1, 2024Feb 1, 2024
    • OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
      Verilog
      412100Updated Jun 14, 2023Jun 14, 2023
    • A configurable SRAM generator
      Rust
      7000Updated May 16, 2023May 16, 2023
    • qspiflash

      Public
      A set of Wishbone Controlled SPI Flash Controllers
      Verilog
      25000Updated May 12, 2023May 12, 2023
    • C++
      0000Updated Jan 17, 2023Jan 17, 2023
    • ramp-core

      Public
      RAMP's out of order RV32G processor, implemented with PyMTL3
      Python
      3200Updated Dec 28, 2022Dec 28, 2022
    • The SystemVerilog style guide for the RAMP framework.
      0000Updated Oct 13, 2022Oct 13, 2022