Trigger Configuration

#Introduction This page will outline information that is obtained with the VANDLE_Pixie16_System_SetupGuide_1.3.pdf. This document was produced at XIA, LLC. by Hui Tan. All of the figures on this page come from the aforementioned document. The information here is valid for the VANDLE firmware released on 02/02/2016.

Nearly all credit for information on this page should go to Hui.

#Firmware Files This firmware is only compatible with the 12-bit 250 MS/s modules.

• System FPGA File : syspixie16_revfvandle_adc250mhz_r34301.bin
• Signal Processing FPGA File : fippixie16_revfvandle_12b250m_r34302.bin
• DSP Code Files :
  • Pixie16DSP_revfvandle_12b250m_r34300.ldr
  • Pixie16DSP_revfvandle_12b250m_r34300.var
  • Pixie16DSP_revfvandle_12b250m_r34300.lst

#Terminology

• System Director Module - The module 0 in Crate 1, Slot 2.
• TrigConfigX - DSP parameters that control the specific setup of the triggering logic.

#Detector Connection Restrictions

1. Always connect VANDLE modules to consecutive Pixie-16 channels, e.g. 0/1, 2/3, etc
2. Always connect beta/valid/neutron detectors to the System Director Module
3. When pairwise coincidence is needed for the beta detectors, the signals should be connected to consecutive Pixie-16 channels, e.g. 0/1, 2/3, etc.

Note: Valid detector types are only allowed in Module 0.

#Logic Signal Generation Each module first makes its local VANDLE pairwise coincidence triggers (maximum 8 pairwise coincidence triggers if all of its 16 channels are connected to VANDLE detectors). It then makes an OR of all of those local VANDLE pairwise coincidence triggers. To output such VANDLE OR trigger to the backplane so that the crate Master module can see such information, set bits 16 to 28 of user module parameter TrigConfig3 (DSP parameter TrigConfig[3]) accordingly. NOTE: Each module should set one and ONLY one bit of bits 16 to 28 of TrigConfig3 to 1, i.e. only select one backplane line to output its OR of 8 VANDLE pairwise coincidence triggers.

After collecting such VANDLE OR triggers from all modules in the crate, the crate Master module then makes an OR of all of those VANDLE OR triggers. We call such OR trigger as the crate level VANDLE_PWA_OR trigger (i.e. VANDLE pairwise AND OR). In a multi-crate system, such VANDLE_PWA_OR trigger is sent from the slave crates to the master crate through the trigger cards, and the System Director Module in the master crate makes a global OR of all the VANDLE_PWA_OR triggers. In the System Director Module to which the beta detectors are connected, the following triggers are also made:

1. OR of Beta pairwise coincidence triggers (BETA_PWA_TRIG_OR)
2. OR of Beta (timing detectors) single triggers
3. OR of Valid single triggers
4. AND of (OR of Beta single triggers) and (OR of Valid single triggers)
5. OR of Neutron detector single triggers

Based on the selection of the source for the beta validation trigger (BETA_VALIDATION_TRIG) by the user, the System Director Module generates the global validation trigger (GLOBAL_TRIG) by first making an OR of the VANDLE_PWA_OR triggers and the OR of Neutron detector single triggers, and then making an AND of such ORed trigger with the beta validation trigger, and outputs such global trigger to all the modules in the system so that they can use it to validate its local data acquisition.

The setup of trigger parameters TrigConfig[2] and TrigConfig[3] largely depends on how the VANDLE and beta detectors are connected to the Pixie-16 modules. However, for bits [28:16] of TrigConfig[3] we must set only one bit to 1 while keeping all other bits at 0 for modules in either a single crate system or multi-crate system.

##Signal Generation on the FPGA The parameters described here are described in more detail in the Timing Adjustment section.

##Logic Diagrams It should be noted that for each of the configurations listed below one can omit the Single Channel Fast Trigger if none are present in the system. In these cases, this part of the logic diagram can be removed and only VANDLE contributes to the VANDLE_PWA_OR.

###Type A This type is an OR of beta detectors that are in coincidence with a VANDLE module OR a single ended neutron detector (e.g. 6Li Glass). This triggering mode was used at the ORNL 2016 VANDLE experiment.

###Type B This trigger type uses an OR of single ended betas in coincidence with an OR of Valid triggers that are in coincidence an OR of VANDLE modules and an OR of neutron detector triggers. This setup was used for the VANDLE-MONA-LISA experiment e11027 at the NSCL.

#Trigger Configurations Gamma-ray detectors do not contribute to the global validation trigger. To tell the system what type of detector is connected to the module you will need to set the appropriate bits of TrigConfig1, TrigConfig2 and TrigConfig3. The user sets these DSP parameters on a per module basis.

Other bits of these parameters are used to control the output of VANDLE and Beta triggers to the backplane, select test signal output, or choose beta validation trigger source.

##Designating Detector Types The following chart demonstrates how to set the bits of TrigConfig1,2,3 appropriately for the desired detector type. Remember that the remaining bits of these configurations are either reserved, or used for other purposes.

##TrigConfig1 Note: Do not modify bits [31:16] of TrigConfig1!

##TrigConfig2 These 4 bits specify a channel number, 0 to 15. This channel's fast trigger will then be used as the group trigger to trigger all 16 channels of the same module at the same time, i.e. the group trigger replaces the local fast trigger of a channel. This is useful for the case where a snapshot of all 16 channels' trace is recorded, regardless whether a given channel has a local fast trigger or not.

##TrigConfig3 The bits [30:29] of TrigConfig3 control the trigger logic. For example, to enable Type B logic you should set bit 29 to 1 and bit 30 to 0. It should be noted that options 00 and 11 are identical, and 00 is suggested for simplicity's sake.

Bit 31 controls what signals can be read out of the front panel of the module . You may read more about this in a dedicated section.

###Backplane Distribution For a given module bits [28:16] of TrigConfig[3] set one and only one bit to 1 while keeping all other bits at 0. Please see the following table as an example.

#Setup of Channel CSRA To require any Pixie-16 channel be gated with a pairwise coincidence trigger (either VANDLE detectors or beta detectors), set bit 13 of DSP parameter ChanCSRA to 1 (i.e. require channel trigger for validation). To require any Pixie-16 channel be gated with the global validation trigger, set bit 11 of DSP parameter ChanCSRA to 1 (i.e. require global trigger for validation).

For beta channels, bit 13 of ChanCSRA should be set to 1 if beta channels require pairwise coincidence, but should be set to 0 if no beta pairwise coincidence is required. For neutron channels, since they are single channel detectors, bit 13 of ChanCSRA should be set to 0. For gamma channels, bit 13 of ChanCSRA should also be set to 0.

NOTE: Channel Control Resgister B (CSRB) is not currently used and should be set to 0 for all modules.

##Recording External Timestamps To enable recording of external clock timestamps in a channel’s event header, set bit 21 of ChanCSRA to 1 in such a channel. This is required for the MoNA experiments where an external ~20 MHz clock signal is input to the System Director Module’s front panel. This can be done by setting bit 21 of ChanCSRA of Channel #0 of the System Director Module to 1 while keeping all other channels’ bit 21 of ChanCSRA to 0. Thus only Channel #0 of System Director Module will record the external clock timestamps in its event header.

#Setup System Director and Crate Master Modules ##Single Crate System

##Two-Crate System

##Module CSRB NOTE: Module CSRA is not currently used and should be set to 0 for all modules.

#Timing Adjustment The following parameters can be adjusted by the user for achieving different timing characteristics.

Fast trigger stretch length

This is the user channel parameter FASTTRIGBACKLEN (DSP parameter FastTrigBackLen). It can be adjusted between 8 ns and 32.76 us. It is used to stretch the fast trigger pulse before such trigger pulse is used to make coincidence or multiplicity decisions. Thus, it is essentially the coincidence window width.

Fast trigger delay length

This is the user channel parameter FtrigoutDelay (DSP parameter FtrigoutDelay). It can be adjusted between 0 ns and 1.016 us. It is used to delay the fast trigger pulse before such trigger pulse is used to make coincidence or multiplicity decisions.

Extern delay

This is the user channel parameter ExternDelayLen (DSP parameter ExternDelayLen). It can be adjusted between 0 ns and 2.040 us. It is used to delay the local fast trigger in order to compensate for the delayed arrival of the channel or global validation triggers.

External trigger stretch length

This is the user channel parameter ExtTrigStretch (DSP parameter ExtTrigStretch). It can be adjusted between 8 ns and 32.760 us. It is used to stretch the external global validation trigger pulse.

Channel trigger stretch length

This is the user channel parameter ChanTrigStretch (DSP parameter ChanTrigStretch). It can be adjusted between 8 ns and 32.760 us. It is used to stretch the channel validation trigger pulse.