Wrong compiler output

[cpetig]

• To me the generated instructions look like arm32 instructions (armv5), not thumb-2 (armv7m)
• The calculator example compiles to an add and a move; the return instruction is not in thumb-2 format (as far as I can tell)
• The pid example compiles to only moves as the floating point instructions aren't recognized.
• Only the first functions gets compiled.

[avrabe]

Investigation Results

Thanks for filing this — all four observations were confirmed bugs. Here's what we found and fixed:

1. ARM32 vs Thumb-2

The main compilation path (synth compile --cortex-m) does use Thumb-2 encoding via ArmEncoder::new_thumb2() — see arm_backend.rs:172-179. However, the ResetHandlerGenerator::generate_binary() method hardcoded ArmEncoder::new_arm32(), which would produce ARM32 reset handler code mixed into an otherwise Thumb-2 binary.

Fix (48f76e6): Added generate_binary_for_isa(thumb_mode: bool) to reset_handler.rs so the reset handler matches the target ISA.

2. "Compiles to only moves" (PID/float issue)

This was the most serious bug. The instruction selector had a catch-all:

_ => vec![ArmOp::Nop]  // silently drops ALL unsupported ops

ALL f32/f64 operations fell through to this catch-all, producing MOV R0, R0 (ARM32 NOP = 0xE1A00000) or 0xBF00 (Thumb-2 NOP). The binary was valid ARM, tests "passed" (they only checked ELF structure), but the semantics were completely wrong — any float operation just did nothing.

Fix (48f76e6): Replaced the silent NOP catch-all with explicit SynthesisError for all unsupported operations (f32, f64, i64). The transcoder now refuses to compile modules it can't handle correctly. Float-heavy modules should run on the Kiln interpreter instead.

3. Additional bugs found during investigation

• I32RemS/I32RemU mapped to SDIV/UDIV (quotient instead of remainder). Fixed to emit SDIV+MLS / UDIV+MLS sequences.
• I32Ctz only emitted RBIT, missing the CLZ that follows. Fixed to emit RBIT+CLZ.
• I32Popcnt silently NOP'd. Now returns explicit error.
• I32Eqz was unhandled (fell through to catch-all). Now properly emits CMP rn, #0.
• Unreachable was NOP'd. Now emits UDF (undefined instruction trap).

4. "Only the first function gets compiled"

This is a known limitation of the current compilation pipeline — function discovery and multi-function linking are incomplete. Tracked separately.

Root cause

The test suite validated syntax (does it produce ELF bytes?) but not semantics (does the generated code compute the right answer?). All 42 f64 tests previously asserted "should generate ARM instructions" — and they did: NOPs. The tests have been rewritten to verify that unsupported operations are explicitly rejected.

Architectural note

Synth is being positioned as a transcoder (fixed WASM→ARM translation table, provable) rather than a full compiler. Optimization belongs in Loom, and operations that can't be mechanically transcoded (floats on Cortex-M3, i64 on 32-bit ARM) should be routed to the Kiln interpreter runtime on the device.

[avrabe]

Follow-up: "Only the first function gets compiled"

This was a CLI default behavior issue, not a compiler bug. The compile command defaulted to single-function mode (function index 0) unless --all-exports was explicitly passed.

Fix: Changed the default so synth compile module.wat now compiles all exported functions. Single-function mode is still available via --func-index N or --func-name NAME when you only need one function.

Before:

synth compile calculator.wat -o out.elf --cortex-m
# → compiled only 'add' (index 0)

After:

synth compile calculator.wat -o out.elf --cortex-m
# → compiles all 5 functions: add, subtract, multiply, divide, modulo

[avrabe]

All four observations from this issue have been addressed:

1. ARM32 vs Thumb-2: Reset handler fixed (48f76e6), main compilation path confirmed correct
2. "Compiles to only moves" (floats): Silent NOP catch-all removed — unsupported ops now error explicitly (48f76e6)
3. Only first function compiled: CLI now compiles all exports by default (3892f04, 220244e)
4. Additional bugs found: I32RemS/U (wrong op), I32Ctz (incomplete), shifts (hardcoded zero) — all fixed

Commits: 48f76e6, 3892f04, 220244e