safety: complete STPA steps 2-4 (control structure, UCAs, loss scenarios)#46
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safety: complete STPA steps 2-4 (control structure, UCAs, loss scenarios)#46
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…ios) Add the remaining STPA analysis artifacts for the synth compiler: - Step 2: Control structure with 6 controllers (instruction selector, peephole optimizer, ARM encoder, ELF builder, ISA validator, Z3 verifier), 3 controlled processes, and 10 control actions. - Step 3: 18 unsafe control actions across all controllers covering providing, not-providing, too-early-too-late, and stopped-too-soon categories. 18 corresponding controller constraints. - Step 4: 12 loss scenarios with causal factors covering inadequate control algorithms, inadequate process models, and sensor failures. - System constraints: 10 system-level safety constraints derived from the hazards defined in Step 1. All files validate with `rivet validate` (PASS, no new errors). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Complex test case (#36): 17 end-to-end control flow tests covering nested blocks, loops with br_if exit, if/else, br_table dispatch, fibonacci, factorial, deeply nested blocks, loop re-entry, call in loop, early return, unreachable traps, and sequential loops. Rivet artifacts for full traceability: - component-model.yaml: 14 artifacts (CM-001..005 system-reqs, CM-TR-001..006 sw-reqs, CM-VER-001..003 verification) tracing WASI Component Model integration with kiln via BA RFC #46 - target-platforms.yaml: 8 artifacts (TP-001..008) capturing Cortex-M4F/M7/M33 targets, STM32F407/nRF52840 board profiles, vector tables, MPU, and Renode emulation platform - zephyr-integration.yaml: 10 artifacts (ZI-001..010) for Zephyr RTOS integration including CMake build, AAPCS compliance, memory domains, calculator app, PID demo, and linker scripts Closes #36 Implements: FR-002 Implements: FR-005 Trace: skip Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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…54) Complex test case (#36): 17 end-to-end control flow tests covering nested blocks, loops with br_if exit, if/else, br_table dispatch, fibonacci, factorial, deeply nested blocks, loop re-entry, call in loop, early return, unreachable traps, and sequential loops. Rivet artifacts for full traceability: - component-model.yaml: 14 artifacts (CM-001..005 system-reqs, CM-TR-001..006 sw-reqs, CM-VER-001..003 verification) tracing WASI Component Model integration with kiln via BA RFC #46 - target-platforms.yaml: 8 artifacts (TP-001..008) capturing Cortex-M4F/M7/M33 targets, STM32F407/nRF52840 board profiles, vector tables, MPU, and Renode emulation platform - zephyr-integration.yaml: 10 artifacts (ZI-001..010) for Zephyr RTOS integration including CMake build, AAPCS compliance, memory domains, calculator app, PID demo, and linker scripts Closes #36 Implements: FR-002 Implements: FR-005 Trace: skip Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Completes the STPA analysis for synth. Step 1 (losses + hazards) was merged in PR #40. This adds:
Total artifacts: 130 (up from 53).
rivet validatepasses with 14 warnings (down from 24).Key traceability example: H-4 (ISA variant mismatch) → UCA-1 (emit FPU on non-FPU target) → LS-1 (incomplete ISA feature database) → SC-4 (ISA variant gating required) — and PR #45 implements exactly this.
Test plan
rivet validatepasses (14 warnings, no errors)rivet statsshows 130 artifacts🤖 Generated with Claude Code