Gimme more registers

qiling/arch/arm.py

@@ -8,11 +8,20 @@
 
 from qiling.const import *
 from .arch import QlArch
-from .arm_const import *
+
+class ARMConst():
+    @property
+    def reg_map(self):
+        reg_map={}
+        for x in dir(arm_const):
+            if "UC_ARM_REG_" in x:
+                reg_map[x.replace("UC_ARM_REG_","").lower()]=eval(x)
+        return reg_map
 
 class QlArchARM(QlArch):
     def __init__(self, ql):
         super(QlArchARM, self).__init__(ql)
+        reg_map = ARMConst().reg_map
         register_mappings = [
             reg_map
         ]

qiling/arch/arm64.py

@@ -8,11 +8,20 @@
 
 from qiling.const import *
 from .arch import QlArch
-from .arm64_const import *
+
+class ARM64Const():
+    @property
+    def reg_map(self):
+        reg_map={}
+        for x in dir(unicorn.arm64_const):
+            if "UC_ARM64_REG_" in x:
+                reg_map[x.replace("UC_ARM64_REG_","").lower()]=eval(x)
+        return reg_map
 
 class QlArchARM64(QlArch):
     def __init__(self, ql):
         super(QlArchARM64, self).__init__(ql)
+        reg_map=ARM64Const().reg_map
 
         register_mappings = [
             reg_map

qiling/arch/mips.py

@@ -8,15 +8,23 @@
 
 from qiling.const import *
 from .arch import QlArch
-from .mips_const import *
+
+class MIPSConst():
+    @property
+    def reg_map(self):
+        reg_map={}
+        for x in dir(mips_const):
+            if "UC_MIPS_REG_" in x:
+                reg_map[x.replace("UC_MIPS_REG_","").lower()]=eval(x)
+        return reg_map
 
 
 class QlArchMIPS(QlArch):
     def __init__(self, ql):
         super(QlArchMIPS, self).__init__(ql)
-
+        reg_map=MIPSConst().reg_map
         register_mappings = [
-            reg_map, reg_map_afpr128
+            reg_map
         ]
 
         for reg_maper in register_mappings:

qiling/debugger/gdb/gdb.py

@@ -20,9 +20,12 @@
 from qiling.arch.x86_const import reg_map_64 as x86_reg_map_64
 from qiling.arch.x86_const import reg_map_misc as x86_reg_map_misc
 from qiling.arch.x86_const import reg_map_st as x86_reg_map_st
-from qiling.arch.arm_const import reg_map as arm_reg_map
-from qiling.arch.arm64_const import reg_map as arm64_reg_map
-from qiling.arch.mips_const import reg_map as mips_reg_map
+from qiling.arch.arm import ARMConst
+from qiling.arch.arm64 import ARM64Const
+from qiling.arch.mips import MIPSConst
+arm64_reg_map=ARM64Const().reg_map
+arm_reg_map=ARMConst().reg_map
+mips_reg_map=MIPSConst().reg_map
 
 GDB_SIGNAL_INT  = 2
 GDB_SIGNAL_SEGV = 11
@@ -85,7 +88,7 @@ def __init__(self, ql, ip, port):
 
         self.gdb.bp_insert(self.entry_point)
 
-        
+
 
         #Setup register tables, order of tables is important
         self.tables = {

qiling/extensions/idaplugin/qilingida.py

@@ -16,13 +16,18 @@
 # Qiling
 from qiling import *
 from qiling.const import *
+from qiling.arch.x86_const import reg_map_16 as x86_reg_map_16
 from qiling.arch.x86_const import reg_map_32 as x86_reg_map_32
 from qiling.arch.x86_const import reg_map_64 as x86_reg_map_64
 from qiling.arch.x86_const import reg_map_misc as x86_reg_map_misc
 from qiling.arch.x86_const import reg_map_st as x86_reg_map_st
-from qiling.arch.arm_const import reg_map as arm_reg_map
-from qiling.arch.arm64_const import reg_map as arm64_reg_map
-from qiling.arch.mips_const import reg_map as mips_reg_map
+from qiling.arch.arm import ARMConst
+from qiling.arch.arm64 import ARM64Const
+from qiling.arch.mips import MIPSConst
+arm_reg_map=ARMConst().reg_map
+arm64_reg_map=ARM64Const().reg_map
+mips_reg_map=MIPSConst().reg_map
+
 from qiling.utils import ql_get_arch_bits
 from qiling import __version__ as QLVERSION
 from qiling.os.filestruct import ql_file
@@ -55,6 +60,7 @@
 from PyQt5 import QtCore, QtWidgets
 from PyQt5.QtWidgets import (QPushButton, QHBoxLayout)
 
+
 QilingHomePage = 'https://www.qiling.io'
 QilingStableVersionURL = 'https://raw.githubusercontent.com/qilingframework/qiling/master/qiling/__version__.py'
 logging.basicConfig(level=logging.INFO, format='[%(levelname)s][%(module)s:%(lineno)d] %(message)s')
@@ -819,14 +825,17 @@ def update(self, ctx):
     @staticmethod
     def get_reg_map(ql:Qiling):
         tables = {
+            QL_ARCH.A8086: list({**x86_reg_map_16, **x86_reg_map_misc}.keys()),
             QL_ARCH.X86     : list({**x86_reg_map_32, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
             QL_ARCH.X8664   : list({**x86_reg_map_64, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
             QL_ARCH.ARM     : list({**arm_reg_map}.keys()),
             QL_ARCH.ARM64   : list({**arm64_reg_map}.keys()),
             QL_ARCH.MIPS    : list({**mips_reg_map}.keys()),
         }
 
-        if ql.archtype == QL_ARCH.X86:
+        if ql.archtype == QL_ARCH.A8086:
+            return tables[QL_ARCH.A8086]
+        elif ql.archtype == QL_ARCH.X86:
             return tables[QL_ARCH.X86]
         elif ql.archtype == QL_ARCH.X8664:
             return tables[QL_ARCH.X8664]