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Introduce “riscv” architecture to qiling#980

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xwings merged 32 commits into
qilingframework:devfrom
cla7aye15I4nd:riscv
Nov 10, 2021
Merged

Introduce “riscv” architecture to qiling#980
xwings merged 32 commits into
qilingframework:devfrom
cla7aye15I4nd:riscv

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@cla7aye15I4nd cla7aye15I4nd commented Nov 4, 2021 •
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riscv architecture for the development of mcu.

Checklist

Which kind of PR do you create?

  • This PR only contains minor fixes.
  • This PR contains major feature update.
  • This PR introduces a new function/api for Qiling Framework.

Coding convention?

  • The new code conforms to Qiling Framework naming convention.
  • The imports are arranged properly.
  • Essential comments are added.
  • The reference of the new code is pointed out.

Extra tests?

  • No extra tests are needed for this PR.
  • I have added enough tests for this PR.
  • Tests will be added after some discussion and review.

Changelog?

  • This PR doesn't need to update Changelog.
  • Changelog will be updated after some proper review.
  • Changelog has been updated in my PR.

Target branch?

  • The target branch is dev branch.

One last thing

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cla7aye15I4nd commented Nov 4, 2021

May be we can add testcases and merge it until new version unicorn (without 'ecall' bug) released.

xwings
xwings reviewed Nov 10, 2021
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Comment thread qiling/utils.py
archendian = QL_ENDIAN.EL
arch = QL_ARCH.RISCV64


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why two line spacing ?

Comment thread qiling/utils.py Outdated
return QL_ARCH.A8086, QL_OS.DOS, QL_ENDIAN.EL

arch, ostype, endian = ql_elf_parse_emu_env(path)
arch, ostype, endian = ql_elf_parse_emu_env(path)
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additional tab ?

@xwings xwings merged commit f51dd88 into qilingframework:dev Nov 10, 2021
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