fixup! target/hexagon: Add a TLB count property #110
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Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The BADVA reg is referred to with the wrong identifier. The CAUSE reg field of SSR is not yet modeled, we will dump the SSR in a subsequent commit. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
…ags() Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
These registers are defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf Refer to §11.9.1 SYSTEM GUEST, §11.9.2 SYSTEM MONITOR. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Also: add nop TCG overrides for break,unpause,fetchbo,dczeroa break: this hardware breakpoint instruction is used with the in-silicon debugger feature, this is not modeled. unpause: this instruction is used to resume hardware threads that are stalled by pause instructions. pause is modeled as a nop, or in RR mode as an EXCP_YIELD. This instruction is safe to ignore. Since cache/prefetch functions are not modeled, dczero and fetchbo are safe to ignore. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This commit provides handlers to generate TCG for guest and system register reads and writes. They will be leveraged by a future commit. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Define the register fields for ssr, schedcfg, stid, bestwait, ccr, modectl, imask, ipendad. Define the fields for TLB entries. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Define TCG overrides for {c,}swi {c,s}iad, iassign{r,w}, {s,g}etimask
instructions.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Define TCG overrides for start, stop, wait, resume instructions. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Co-authored-by: Sid Manning <sidneym@quicinc.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Marco Liebel <mliebel@quicinc.com>
The number of parameters for `DEF_MACRO` changed and needed to be updated too. Signed-off-by: Marco Liebel <mliebel@quicinc.com>
Signed-off-by: Marco Liebel <mliebel@quicinc.com>
Signed-off-by: Marco Liebel <mliebel@quicinc.com>
Signed-off-by: Marco Liebel <mliebel@quicinc.com>
A single mapping is made by qct-qtimer.c and the extraneous region caused confusion. Signed-off-by: Sid Manning <sidneym@quicinc.com>
* TODO: forward the instruction tag to the unimp log? * TODO: why do we need_env() for these? * TODO: filter out some attributes? These instructions are unimplemented for now, they are used by h2.
Signed-off-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Sid Manning <sidneym@quicinc.com>
| #define THREADS_MAX 8 | ||
| #define VECTOR_UNIT_MAX 8 | ||
| #define MAX_TLB_ENTRIES 1024 | ||
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Should we also remove SLOTS_MAX above?
quic-mathbern
approved these changes
Mar 12, 2025
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Have we already removed |
Not yet. I'll take this open or just-merged PRs and cherry-pick the changes downstream tomorrow. But Brian has a good point @SidManning , I think we should make an habit of always creating the equivalent MR downstream when we are applying these changes from review comments. I'll try to do that too |
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These changes are now incorporated into |
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