Useful helpers for Bluespec developers.
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This project provides helper scripts that can be used to create Bluespec projects. The generated Makefile supports
- Compile and simulate using Bluesim
- Compile and simulate using
bscsupported Verilog simulators - Build IP-XACT Packets for use in Xilinx Vivado
- Python 3
- Bluespec Compiler
To get a local copy up and running follow these simple steps.
Have the bluespec compiler and Python 3 installed.
- Clone the repo
git clone https://github.com/esa-tu-darmstadt/BSVTools.git- Create a new directory for the Bluespec project
- Run
path/to/BSVTools/bsvNew.py PROJECT_NAME - (Optional) Add libraries to the created library directory (e.g. BlueAXI or BlueLib)
The script creates a number of basic Bluespec modules that can be extended as desired.
BSVTools stores device specific information in the file .bsv_tools. By default this file is excluded from Git using .gitignore.
A new .bsv_tools file can be created using:
- Run
path/to/BSVTools/bsvAdd.py
Simulate using Bluesim
makeSimulate using Verilog (Modelsim/Questasim by default)
make SIM_TYPE=VERILOGBuild IP-XACT packet (Needs Vivado in path):
make SIM_TYPE=VERILOG ipFor more examples, please refer to the Documentation
See the open issues for a list of proposed features (and known issues).
Contributions are what make the open source community such an amazing place to be learn, inspire, and create. Any contributions you make are greatly appreciated.
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/AmazingFeature) - Commit your Changes (
git commit -m 'Add some AmazingFeature') - Push to the Branch (
git push origin feature/AmazingFeature) - Open a Pull Request
Distributed under the MIT License. See LICENSE for more information.
Embedded Systems and Applications Group - https://www.esa.informatik.tu-darmstadt.de
Project Link: https://github.com/esa-tu-darmstadt/BSVTools