Add Verilog, Systemverilog, and VHDL language extension

[dadlerj]

Feature request description

From a user:

I've looked at sourcegraph before but it seems to have had some of churn on the language support issue. Previously the basic-code-intell worked out of the box for these languages (Verilog, Systemverilog and VHDL). Now, this useful feature has been dropped. I dug a little and see that it might be possible for me to add these languages but I'm afraid the update to the basic-code-intell stuff might be just out of my reach. The doc on that repo is a bit confusing. If I read it right , basic code intell uses universal-ctags under the hood (which I've used before) but I don't quite understand how to configure it on a per-language basis.

Seems like .v, .vh, .svh, and .vhdl are the file extensions covered here...

[mpettigr]

I'm the "user" from above. The typical/canonical file extensions for these 3 languages are:

VHDL -> .vhd, .vhdl
Verilog -> .v, .vh
SystemVerilog -> .sv, .svh

For extra credit, :-) , Tcl is the de facto scripting language in our field (FPGA/ASIC development) so adding Tcl would definitely be a huge plus as well. The only file extensions I'm aware of in Tcl are .tcl and .test

Any help is greatly appreciated. Thanks!

[mpettigr]

Hi guys,

Any update on adding VHDL, Verilog, SystemVerilog and Tcl basic language support to sourcegraph. Can you give guidance on how I might contribute as I really would love to see these languages added? Thanks.

[chrismwendt]

Apologies for the delayed response - here's how to add a new language:

• Add a new language entry to basic-code-intel (e.g. Clojure is defined at https://github.com/sourcegraph/sourcegraph-basic-code-intel/blob/346c2d728f7fecc0cf2ee3d3fb9d19d0aeaf7200/languages.ts#L402)
• Add the language name to the command line arguments to universal-ctags https://github.com/sourcegraph/sourcegraph/blob/21efc6844838e773b9a8f4a7ba1d5628e8076984/cmd/symbols/internal/pkg/ctags/parser.go#L71