[BUG] cavs: icl: core 3 must be powered on startup by the driver

[mmaka1]

Describe the bug
Since the DSP starts at full throttle (HP-RO 400 MHz is used as a clock source), the driver should set SPA for core3 in addition to core0 in order to propagate required notifications to other units. This should be done "silently", run-time environment for core3 is not required at this point, so the FW does not need to know about this.

In future, when more power optimizations will be implemented for icl, the FW will notify the driver (some new pwr state changed notification) when switching to LP-RO 120 MHz and back and the driver may toggle core3 SPA accordingly.

[plbossart]

@mmaka1 care to provide more details? We see random IPC and underflows on ICL w/ SoundWire, if there is a connection.

[lgirdwood]

@plbossart @ranj063 has anyone tried this yet ?

[ranj063]

@lgirdwood I dont think we've tried it yet. I think Pierre asked for more details but @mmaka1 hasnt replied yet.

At the moment the code loading sequence powers up all 4 cores before loading the FW. Not sure what Marcin means here and when Core 3 should be powered up precisely.

[lbetlej]

@ranj063 I'll get back to you once SW/FW programming sequence is finalized for scenarios that require HP Ring Oscillator (400 MHz) clock. Could you confirm current implementation in the driver for initial boot:

1. Set SPA(0..PLATFORM_CORE_COUNT) bit
2. Wait for CPA (0..PLATFORM_CORE_COUNT) bit
3. Wait for FW ready
4. SPA is not set to 0 for cores (1..PLATFORM_CORE_COUNT) -> all cores are up ?

[tlauda]

@lbetlej Should we move this to linux repo, since it looks like additional work for kernel?