[APL][GLK] harden: power-gating and clock gating needs to be disabled during firmware download

[wenqingfu]

No.2 sub-task of #87.

[zhuyingjiang]

I think this has already been supported.

[mengdonglin]

@plbossart Can this issue be closed?

[plbossart]

I'd like a comparison with the Skylake driver (including non-upstreamed parts). The ask for all this was to doubled-check what was done in the past and make sure all known recommended sequences are supported by SOF.

[zhuyingjiang]

@plbossart The clock/power gating for firmware download is done by PR #249 9e1dec6.
I will submit a PR for clock/power gating for suspend/resume, and also the misc clock gating(backbone).

[zhuyingjiang]

the misc clock gating part is fixed by #877.
as suggested by Lech's mail:

1.  PGCTL has a reversed logic. PGCTL.ADSPPG == 1 means that power gating is disabled
   

=> done by #249
2. CGCTL.MISCBDCGE needs to be disabled during controller reset
=>done by #877
mark as fixed.