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Fix/checkpatch #55

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Merged
plbossart merged 4 commits into from
Jul 23, 2018
Merged

Fix/checkpatch #55

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5b3e2d5
[SQUASHME] ASoC: SOF: Intel: hda: harden macro parameters
plbossart Jul 23, 2018
12d6b26
[SQUASHME] ASoC: SOF: intel: hda-pcm: harden macro parameters
plbossart Jul 23, 2018
b53ea4c
[SQUASHME] ASoC: SOF: Intel: shim.h: harden macro parameters
plbossart Jul 23, 2018
d21d006
[SQUASHME] ASoC: SOF: Intel: hda-dai: remove spurious lines
plbossart Jul 23, 2018
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2 changes: 0 additions & 2 deletions sound/soc/sof/intel/hda-dai.c
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Original file line number Diff line number Diff line change
Expand Up @@ -110,5 +110,3 @@ struct snd_soc_dai_driver skl_dai[] = {
SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
},
};


10 changes: 5 additions & 5 deletions sound/soc/sof/intel/hda-pcm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,11 +34,11 @@
#include "../ops.h"
#include "hda.h"

#define SDnFMT_BASE(x) (x << 14)
#define SDnFMT_MULT(x) ((x - 1) << 11)
#define SDnFMT_DIV(x) ((x - 1) << 8)
#define SDnFMT_BITS(x) (x << 4)
#define SDnFMT_CHAN(x) (x << 0)
#define SDnFMT_BASE(x) ((x) << 14)
#define SDnFMT_MULT(x) (((x) - 1) << 11)
#define SDnFMT_DIV(x) (((x) - 1) << 8)
#define SDnFMT_BITS(x) ((x) << 4)
#define SDnFMT_CHAN(x) ((x) << 0)

static inline u32 get_mult_div(struct snd_sof_dev *sdev, int rate)
{
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4 changes: 2 additions & 2 deletions sound/soc/sof/intel/hda.h
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Expand Up @@ -119,7 +119,7 @@
#define HDA_DSP_DRSM_BAR 3
#define HDA_DSP_BAR 4

#define SRAM_WINDOW_OFFSET(x) (0x80000 + x * 0x20000)
#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)

#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)

Expand Down Expand Up @@ -266,7 +266,7 @@
* Mask for a given number of cores
* nc = number of supported cores
*/
#define SOF_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0)
#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)

/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
#define CNL_DSP_IPC_BASE 0xc0
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10 changes: 5 additions & 5 deletions sound/soc/sof/intel/shim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@
#define SHIM_CSR_RST (0x1 << 1)
#define SHIM_CSR_SBCS0 (0x1 << 2)
#define SHIM_CSR_SBCS1 (0x1 << 3)
#define SHIM_CSR_DCS(x) (x << 4)
#define SHIM_CSR_DCS(x) ((x) << 4)
#define SHIM_CSR_DCS_MASK (0x7 << 4)
#define SHIM_CSR_STALL (0x1 << 10)
#define SHIM_CSR_S0IOCS (0x1 << 21)
Expand Down Expand Up @@ -95,7 +95,7 @@
#define SHIM_BYT_IPCD_BUSY ((u64)0x1 << 63)

/* CLKCTL */
#define SHIM_CLKCTL_SMOS(x) (x << 24)
#define SHIM_CLKCTL_SMOS(x) ((x) << 24)
#define SHIM_CLKCTL_MASK (3 << 24)
#define SHIM_CLKCTL_DCPLCG BIT(18)
#define SHIM_CLKCTL_SCOE1 BIT(17)
Expand All @@ -106,11 +106,11 @@
#define SHIM_CSR2_SDFD_SSP1 BIT(2)

/* LTRC */
#define SHIM_LTRC_VAL(x) (x << 0)
#define SHIM_LTRC_VAL(x) ((x) << 0)

/* HMDC */
#define SHIM_HMDC_HDDA0(x) (x << 0)
#define SHIM_HMDC_HDDA1(x) (x << 7)
#define SHIM_HMDC_HDDA0(x) ((x) << 0)
#define SHIM_HMDC_HDDA1(x) ((x) << 7)
#define SHIM_HMDC_HDDA_E0_CH0 1
#define SHIM_HMDC_HDDA_E0_CH1 2
#define SHIM_HMDC_HDDA_E0_CH2 4
Expand Down