-
Notifications
You must be signed in to change notification settings - Fork 140
ASoC: SOF: ipc4-pcm: fix start offset calculation for chain DMA #5507
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
ASoC: SOF: ipc4-pcm: fix start offset calculation for chain DMA #5507
Conversation
Assumption that chain DMA module starts the link DMA when 1ms of data is available from host is not correct. Instead the firmware chain DMA module fills the link DMA with initial buffer of zeroes and the host and link DMAs are started at the same time. This results in a small error in delay calculation. This can become a more severe problem if host DMA has delays that exceed 1ms. This results in negative delay to be calculated and bogus values reported to applications. This can confuse some applications like alsa_conformance_test. Fix the issue by correctly calculating the firmware chain DMA preamble size and initializing the start offset to this value. Fixes: a1d203d ("ASoC: SOF: ipc4-pcm: Enable delay reporting for ChainDMA streams") Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
|
Issue found while developing #5499 |
| * alignment that is not known to host. | ||
| */ | ||
| time_info->stream_start_offset = substream->runtime->rate / MSEC_PER_SEC; | ||
| int pre_ms = SOF_IPC4_CHAIN_DMA_BUF_SIZE_MS * 5 / 2 + 1; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
FW code calculates above as '2 * 5 / 2', convert to bytes and aligns up to DMA transfer size. We could calculate this exactly, but not sure if it will add value here.
ujfalusi
left a comment
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thanks @kv2019i for diving into the details and fixing this!
|
Let me mark with a DNM briefly. I need to double check this after a new chain-DMA issue found on FW side. Will link to the PR once it is ready. |
|
Cleared the DNM, this is valid in its current form. I double-checked the behaviour from host/link DMA status dumps during the startup sequence and it matches the patch now. |
Assumption that chain DMA module starts the link DMA when 1ms of data is available from host is not correct. Instead the firmware chain DMA module fills the link DMA with initial buffer of zeroes and the host and link DMAs are started at the same time.
This results in a small error in delay calculation. This can become a more severe problem if host DMA has delays that exceed 1ms. This results in negative delay to be calculated and bogus values reported to applications. This can confuse some applications like alsa_conformance_test.
Fix the issue by correctly calculating the firmware chain DMA preamble size and initializing the start offset to this value.
Fixes: a1d203d ("ASoC: SOF: ipc4-pcm: Enable delay reporting for ChainDMA streams")