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[BUG] Interrupts from PMC are not masked on cavs platfroms #2908

@lbetlej

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@lbetlej

Describe the bug
Bit #5 in REG_IRQ_IL2MD(0): 0xb00050 is not set. Expectation is that the bit will be set for all DSP cores.
Since in a default mask bit #5 is set (#define REG_IRQ_IL2MD_ALL 0x03F181F0) there is a need to investigate how the bit is cleared.

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TGLApplies to Tiger LakebugSomething isn't working as expectedstaleIssue/PR marked as stale and will be closed after 14 days if there is no activity.

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