[BUG] [TGL] HDA controller reset fails in reboot tests

[sathya-nujella]

[Bug cloned from]
thesofproject/linux#2571

DUT: TGL Chrome DUT with Max98373_RT5682 I2S
BIOS: Coreboot

Issue:
Sound card creation failed.

TEST SCENARIO:
Random scenarios.
one such scenario is:
Boot DUT -> mount file system -> reboot few times to see error.

More details:
ISSUE REPRODUCED WITH:
SOF branch: tgl-011-drop-stable top commit: 27aab4f

After reverting the below patch, issue is not seen in 100 reboot cycles (need to continue further tests):
tgl: enable WOVCRO clock
Reverted the patch: 75561a9

[kv2019i]

Hit on Ubuntu Linux device as well. FW 010-hotfix.

@abonislawski Would it be possible to change to a higher clock whenever DSP is stopped? It would seem that if clock is left at WOVCRO and system is reset, HDA controller will not come out of reset anymore (with high repro rate).

[keqiaozhang]

we also observed this issue when testing sof-011-drop-stable branch, I tried to test more on TGL-RVP-HDA this morning and found that the reproduction rate is about 30%。

[mwasko]

Is the FW even loaded when this reboot issue occurs?

[mengdonglin]

Thank you @kv2019i and @keqiaozhang

@abonislawski @mwasko Please note this issue can also be reproduced on branch tgl-010-drop-stable and tgl-010-hot-fix-1, it's not a branch specific issue for tgl-011-drop-stable

[lgirdwood]

@sathya-nujella @kv2019i I assume FW with reverted 75561a9 has booted at least once (without a power OFF - due to the reproduction rates) during your testing.
@mwasko it does seem that FW is booting, but I wonder if weed to force the clock in our FW D3 code to be sure (since it looks like the clock setting may survive a DSP D3).

[abonislawski]

@kv2019i @lgirdwood do you think disabling wovcro in ipc_pm_context_save() (pm_prepare_D3) would be a good idea to test?
EDIT: but we already did on wakeup

[lgirdwood]

@kv2019i @lgirdwood do you think disabling wovcro in ipc_pm_context_save() (pm_prepare_D3) would be a good idea to test?
EDIT: but we already did on wakeup

@abonislawski it's probably worth trying (and remember any delay).

[kv2019i]

@lgirdwood wrote:

@sathya-nujella @kv2019i I assume FW with reverted 75561a9 has booted at least once (without a power OFF - due to the reproduction rates) during your testing.

Correct. DSP is loaded at least once, and then a sw-reset (system reboot) is performed.