[BUG] THD value is larger than acceptable value

[wszypelt]

Describe the bug
Issue was found in:
[ICL]
11_03_TestSrcSamplingRateChange16000Hz32b32b8ch Repro: 1/75
11_03_TestSrcSamplingRateChange48000Hz32b32b4ch Repro: 1/75
[APL]
11_03_TestSrcSamplingRateChange48000Hz32b32b4ch Repro: 1/75

Topology

                plb_ppl
                +--------------------------------+
    +------+    | +---+  +- -+  +---+  +-------+ |
    | Host |----->|Buf|->|Src|->|Buf|->|SSP Dai|---+
    +------+    | +---+  +-- +  +---+  +-------+ | |
                +--------------------------------+ |
                                                   |
                cap_ppl                            |
                +------------------+               |
    +------+    | +---+  +-------+ |               |
    | Host |<-----|Buf|<-|SSP Dai|<----------------+
    +------+    | +---+  +-------+ |
                +------------------+

To Reproduce
Run tests with Diagnostic driver:
11_03_TestSrcSamplingRateChange16000Hz32b32b8ch
11_03_TestSrcSamplingRateChange48000Hz32b32b4ch
With options --playback-iterations=75

Reproduction Rate
1/75

Environment

1. Branch name and commit hash of the 2 repositories: sof (firmware/topology) and linux (kernel driver).
   • SOF BRANCH: main HASH: 37d97d4
2. Name of the platform(s) on which the bug is observed.
   • Platform: ICL RVP, APL RVP
3. Test environment:
   BRANCH: master HASH: 7bc54a9c53346cea3dfc5bdedbc6a02e39597193

Screenshots or console output
ICL 11_03_TestSrcSamplingRateChange16000Hz32b32b8ch

ICL 11_03_TestSrcSamplingRateChange48000Hz32b32b4ch

APL 11_03_TestSrcSamplingRateChange48000Hz32b32b4ch

ICL_11_03_16000Hz.zip
ICL_11_03_48000Hz.zip
APL_11_03.zip

[lgirdwood]

@wszypelt this looks like a DMA R/W race, but it's really difficult to tell which pipeline and whether it's related to ASRC or SRC. Can you try and isolate this further. I would also like to see if a volume on capture pipeline fixes this and bridges the DMAs.

[wszypelt]

@lgirdwood I edited the bug and left only the SRC pipeline. It should be noted that with these tests,
we convert various input formats on one topology and there is 1 output format.
Simultaneous playback and capture on external loopback (same SSP) with signal verification.
Playback pipeline contains SRC component and plays audio formats with different frequencies.
Subsequent input formats are run without destroying the current topology.
I'm not sure this answers your question. If not, please ask.

[lgirdwood]

Duplicate of simpler #4076

[kkarask]

Glitches are visible in the capture stream when SRC component is in playback and capture pipeline.

Tests which failed: 11_02_TestSrcSimpleCapture48000On16000Hz32b32b4ch and 11_01_TestSrcSimple16000On48000Hz32b32b4ch witch reproduction rate 1/75.

[lgirdwood]

@kkarask can you alos test this with #4471 locally. Thanks, we think they may all be related.

[kkarask]

@lgirdwood I run tests with SRC component with #4471 and found fails:

• test: 11_01_TestSrcSimple16000On48000Hz32b32b8ch
  glitch with reproduction rate: 1/100.
  

• test: 11_01_TestSrcSimple16000On48000Hz24b32b4ch
  glitch with reproduction rate: 1/100