[BUG] Memory Leak on Secondary Core Power Cycle

[tmleman]

Describe the bug
A regression has been detected in the power flow code, introduced by commit 5f1e690, causing a memory leak on multicore platforms using Zephyr as the RTOS. The issue manifests as repeated memory allocations for secondary cores that are not freed upon powering down. This results in a gradual depletion of available memory, eventually leading to a firmware exception notification from the DSP. The problem was first identified on the LunarLake platform and is likely to affect other multicore platforms due to the shared power flow code.

To Reproduce
Steps to reproduce the behavior:

1. Power up all secondary cores of the DSP on a multicore platform (e.g., LunarLake).
2. Power down all the secondary cores.
3. Repeat steps 1 and 2 until a firmware exception notification is received from the DSP.

Reproduction Rate
The issue is reproducible 10/10 times when following the above manual sequence on the LunarLake platform. The reproduction rate is expected to be consistent across other multicore platforms using Zephyr as the RTOS.

Expected behavior
Upon powering down the secondary cores, the system should either release the resources allocated during the power-up phase or ensure that they are reused during the next power-up.

Impact
This memory leak is a critical issue that leads to resource exhaustion and potential DSP panic after an extended number of power cycles. It is a showstopper for the reliability and stability of the DSP on all affected multicore platforms.

Environment
* SOF: main
* Platform: LunarLake (and potentially all multicore platforms using Zephyr RTOS)