DMIC and headset MIC LED support on sof-icl-rt711-rt1308-rt715

tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4

@@ -49,7 +49,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
 
 # Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
 # Schedule 48 frames per 1000us deadline on core 0 with priority 0
-PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
+PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
 	2, 1, 2, s32le,
 	1000, 0, 0,
 	48000, 48000, 48000)
@@ -71,7 +71,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
 
 # Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le.
 # Schedule 48 frames per 1000us deadline on core 0 with priority 0
-PIPELINE_PCM_ADD(sof/pipe-highpass-capture.m4,
+PIPELINE_PCM_ADD(sof/pipe-highpass-switch-capture.m4,
 	5, 4, 2, s32le,
 	1000, 0, 0,
 	48000, 48000, 48000)

tools/topology/sof-icl-rt711-rt1308-rt715.m4

@@ -42,7 +42,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
 
 # Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
 # Schedule 48 frames per 1000us deadline on core 0 with priority 0
-PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
+PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
 	2, 1, 2, s32le,
 	1000, 0, 0,
 	48000, 48000, 48000)
@@ -63,7 +63,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
 
 # Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le.
 # Schedule 48 frames per 1000us deadline on core 0 with priority 0
-PIPELINE_PCM_ADD(sof/pipe-highpass-capture.m4,
+PIPELINE_PCM_ADD(sof/pipe-highpass-switch-capture.m4,
 	5, 4, 2, s32le,
 	1000, 0, 0,
 	48000, 48000, 48000)

tools/topology/sof/pipe-highpass-switch-capture.m4

@@ -0,0 +1,134 @@
+# IIR highpass filter, volume/switch control, and PCM
+#
+# Pipeline Endpoints for connection are :-
+#
+#  host PCM_C <-- B0 <-- Volume <-- B1 <-- EQ_IIR <-- B2 <-- source DAI0
+
+# Include topology builder
+include(`utils.m4')
+include(`buffer.m4')
+include(`pcm.m4')
+include(`pga.m4')
+include(`dai.m4')
+include(`mixercontrol.m4')
+include(`pipeline.m4')
+include(`bytecontrol.m4')
+include(`eq_iir.m4')
+
+#
+# Controls
+#
+# Volume Mixer control with max value of 32
+C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID,
+	CONTROLMIXER_OPS(volsw,
+		256 binds the mixer control to volume get/put handlers,
+		256, 256),
+	CONTROLMIXER_MAX(, 80),
+	false,
+	CONTROLMIXER_TLV(TLV 80 steps from -50dB to +30dB for 1dB, vtlv_m50s1),
+	Channel register and shift for Front Left/Right,
+	LIST(`	', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
+
+C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID,
+	CONTROLMIXER_OPS(volsw,
+		259 binds the mixer control to switch get/put handlers,
+		259, 259),
+	CONTROLMIXER_MAX(max 1 indicates switch type control, 1),
+	false,
+	,
+	Channel register and shift for Front Left/Right,
+	LIST(`	', KCONTROL_CHANNEL(FL, 2, 0), KCONTROL_CHANNEL(FR, 2, 1)),
+	"1", "1")
+#
+# Volume Configuration
+#
+
+define(MY_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID))
+define(MY_PGA_CONF, concat(`pga_conf_', PIPELINE_ID))
+W_VENDORTUPLES(MY_PGA_TOKENS, sof_volume_tokens,
+LIST(`		', `SOF_TKN_VOLUME_RAMP_STEP_TYPE	"0"'
+     `		', `SOF_TKN_VOLUME_RAMP_STEP_MS		"400"'))
+
+W_DATA(MY_PGA_CONF, MY_PGA_TOKENS)
+
+#
+# IIR configuration
+#
+
+include(`eq_iir_coef_highpass_40hz_0db_48khz.m4')
+
+# EQ Bytes control with max value of 255
+define(MY_EQIIR_BYTES, concat(`eqiir_bytes_', PIPELINE_ID))
+C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID,
+	CONTROLBYTES_OPS(bytes,
+		258 binds the mixer control to bytes get/put handlers,
+		258, 258),
+	CONTROLBYTES_EXTOPS(
+		258 binds the mixer control to bytes get/put handlers,
+		258, 258),
+	, , ,
+	CONTROLBYTES_MAX(, 304),
+	,
+	EQIIR_HP40HZ0dB48K_priv)
+
+#
+# Components and Buffers
+#
+
+# Host "Highpass Capture" PCM
+# with 0 sink and 2 source periods
+W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2)
+
+# "Volume" has 2 sink and 2 source periods
+W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, MY_PGA_CONF,
+	LIST(`		', "PIPELINE_ID Master Capture Volume",
+	"PIPELINE_ID Master Capture Switch"))
+
+# "EQ_IIR 0" has 2 sink and x source periods
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS,
+	LIST(`		', "MY_EQIIR_BYTES"))
+
+# Capture Buffers
+W_BUFFER(0, COMP_BUFFER_SIZE(2,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
+	COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_HOST_MEM_CAP)
+W_BUFFER(1, COMP_BUFFER_SIZE(2,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
+	COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_HOST_MEM_CAP)
+W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
+	COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS,
+	COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_DAI_MEM_CAP)
+
+#
+# Pipeline Graph
+#
+#  host PCM_P <-- B0 <-- Volume 0 <-- B1 <-- EQ_IIR 0 <-- B2 <-- sink DAI0
+
+P_GRAPH(pipe-pass-vol-capture-PIPELINE_ID, PIPELINE_ID,
+	LIST(`		',
+	`dapm(N_PCMC(PCM_ID), N_BUFFER(0))',
+	`dapm(N_BUFFER(0), N_PGA(0))',
+	`dapm(N_PGA(0), N_BUFFER(1))',
+	`dapm(N_BUFFER(1), N_EQ_IIR(0))',
+	`dapm(N_EQ_IIR(0), N_BUFFER(2))'))
+
+#
+# Pipeline Source and Sinks
+#
+indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(2))
+indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
+
+#
+# PCM Configuration
+#
+
+PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE',
+	PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS,
+	2, 16, 192, 16384, 65536, 65536)
+
+undefine(`MY_PGA_TOKENS')
+undefine(`MY_PGA_CONF')
+undefine(`MY_EQIIR_BYTES')

tools/topology/sof/pipe-volume-switch-capture.m4

@@ -0,0 +1,89 @@
+# Passthrough with volume/switch Pipeline and PCM
+#
+# Pipeline Endpoints for connection are :-
+#
+#  host PCM_C <-- B0 <-- Volume 0 <-- B1 <-- source DAI0
+
+# Include topology builder
+include(`utils.m4')
+include(`buffer.m4')
+include(`pcm.m4')
+include(`pga.m4')
+include(`dai.m4')
+include(`mixercontrol.m4')
+include(`pipeline.m4')
+
+#
+# Controls
+#
+# Volume Mixer control with max value of 32
+C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID,
+	CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
+	CONTROLMIXER_MAX(, 80),
+	false,
+	CONTROLMIXER_TLV(TLV 80 steps from -50dB to +30dB for 1dB, vtlv_m50s1),
+	Channel register and shift for Front Left/Right,
+	LIST(`	', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
+
+C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID,
+	CONTROLMIXER_OPS(volsw, 259 binds the mixer control to switch get/put handlers, 259, 259),
+	CONTROLMIXER_MAX(max 1 indicates switch type control, 1),
+	false,
+	,
+	Channel register and shift for Front Left/Right,
+	LIST(`	', KCONTROL_CHANNEL(FL, 2, 0), KCONTROL_CHANNEL(FR, 2, 1)),
+	"1", "1")
+
+#
+# Volume Configuration
+#
+
+W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens,
+LIST(`		', `SOF_TKN_VOLUME_RAMP_STEP_TYPE	"0"'
+     `		', `SOF_TKN_VOLUME_RAMP_STEP_MS		"250"'))
+
+W_DATA(capture_pga_conf, capture_pga_tokens)
+
+#
+# Components and Buffers
+#
+
+# Host "Passthrough Capture" PCM
+# with 0 sink and 2 source periods
+W_PCM_CAPTURE(PCM_ID, Passthrough Capture, 0, 2)
+
+# "Volume" has x source and 2 sink periods
+W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, capture_pga_conf, LIST(`		', "PIPELINE_ID Master Capture Volume", "PIPELINE_ID Master Capture Switch"))
+
+# Capture Buffers
+W_BUFFER(0, COMP_BUFFER_SIZE(2,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_HOST_MEM_CAP)
+W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS,
+	COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_DAI_MEM_CAP)
+
+#
+# Pipeline Graph
+#
+#  host PCM_P <-- B0 <-- Volume 0 <-- B1 <-- sink DAI0
+
+P_GRAPH(pipe-pass-vol-capture-PIPELINE_ID, PIPELINE_ID,
+	LIST(`		',
+	`dapm(N_PCMC(PCM_ID), N_BUFFER(0))',
+	`dapm(N_BUFFER(0), N_PGA(0))',
+	`dapm(N_PGA(0), N_BUFFER(1))'))
+
+#
+# Pipeline Source and Sinks
+#
+indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(1))
+indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Capture PCM_ID)
+
+#
+# PCM Configuration
+#
+
+PCM_CAPABILITIES(Passthrough Capture PCM_ID, `S32_LE,S24_LE,S16_LE',
+	PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS,
+	2, 16, 192, 16384, 65536, 65536)