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Testbench add process components support#2510

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lgirdwood merged 5 commits intothesofproject:masterfrom
singalsu:testbench_load_process
Mar 20, 2020
Merged

Testbench add process components support#2510
lgirdwood merged 5 commits intothesofproject:masterfrom
singalsu:testbench_load_process

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@singalsu singalsu commented Mar 9, 2020

Here's a cleaned up and more complete version of testbench PR. It consists of these commits:

  • Testbench: Add processing component load
  • Testbench: Fix possible uninitialized use of variable ret
  • Testbench: Build topology parser with debug symbols
  • Tools: Test: Cleanup component run scripts
  • Topology: Fix in EQ only pipelines with macro PIPELINE_SINK

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General, components can support > controls (use different names). Also we need to de-duplicate. Please also add more inline comments.

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This looks like we are starting to duplicate a lot of component loading code. Can we make this all generic.

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I simplified the controls load / ignore from previous version but otherwise I didn't see similar flows. There's always some component specifics.

@singalsu singalsu force-pushed the testbench_load_process branch from a934b18 to a1006c3 Compare March 16, 2020 17:38
@singalsu singalsu changed the title [RFC] Testbench add process components support Testbench add process components support Mar 16, 2020
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General, components can support > controls (use different names). Also we need to de-duplicate. Please also add more inline comments.

I didn't yet see such cases so I could not test. EQs and volume had only one control. An error is reported if there's more though it's not what you recommended.

I tried to seek for de-duplication but it didn't look straightforward. The topology handler and loader in kernel sure is nicer than this. A bigger repair could reuse more from there.

I'd like to pursue more important things like building a simplified testbench (statically linked, possibly remove fseeks) for xt-run/dbg environment.

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I tested this with the dc blocker (PR #2462) as well. It works fine! Once this is merged, I will open a new PR with the changes to make this work with DCB.

fyi @cujomalainey

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singalsu commented Mar 17, 2020

@sebcarlucci Wow, that's great news! Thanks for testing!

I've so far run some components with the SRC test script, e.g. "src_test(24, 24, 48000, 48000)" with src_run.sh edited to pass "eq-iir" instead of "src" to comp_run.sh. Many of the measurements done for SRC can be applied for any processing. I will upstream dedicated EQ test scripts later to check that the measured response matches theoretical response defined by the blob.

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SOFCI TEST

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@singalsu can you follow up here with the CI results. It seems merge is blocked on CI atm.

This patch adds to testbench capability to run pipelines with EQ_IIR
and EQ_FIR components. The component is configured with the topology
embedded configuration blob when instantiated with new().

The load of volume component has been enhanced to parse volume tokens and
compute the min and max volume parameters.

The topology parsing and component library load has been changed to
support processing component load and extracting of control private
data. The testbench build has been changed to create libraries
for EQ components.

The testbench command line parsing has been improved to return
error for invalid library request.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This patch fixes the read_samples_32() function in file component.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This patch adds compilation with -g. Optimization -O was added to get
optimization that preserves sane debugging with gdb. This component
is not critical for speed in simulation.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
The src_run.sh is converted into a generic component run script
that is called by new simple component specific scripts asrc_run.sh,
eqfir_run.sh, eqiir_run.sh, src_run.sh, and volume_run.sh.

Note: The testbench does not yet have fully working capture support
so the direction is not exposed yet.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This patch fixes the buffer to define as PIPELINE_SINK. The
upper level topologies do not use these topologies so there has
not been related errors. However test pipelines were impacted.

Also the PIPELINE_PCM defined name is made more generic. It can
be whatever and not just high-pass type.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
@singalsu singalsu force-pushed the testbench_load_process branch from a1006c3 to 426b313 Compare March 19, 2020 11:52
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The patch check reports some things those are not relevant for testbench

  • Does not understand "FILE *handle";
  • There's no memcpy_s() in C library
  • Two long strings lines in shell scripts for usage
  • One long shell script line define the topology file name to use. The test topology file names are rather long.

The sof-ci/jenkins/pr-device-test is not yet completed

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SOFCI TEST

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@lgirdwood Should I push this PR again to get jenkins test executed? I think only the CI checkpatch report is valid.

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jenkins CI - known issues.
internal CI - unrelated test.

@lgirdwood lgirdwood merged commit 26ea50e into thesofproject:master Mar 20, 2020
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@wwittbrx fyi I've very occasionally seen this error. I'm pretty sure it cant be related to this ?

2020-03-19 23:30:17=> Configure SOF
2020-03-19 23:30:17     => Environment initialization
2020-03-19 23:30:17     => Loading base firmware
2020-03-19 23:30:18=> Enabling DMA trace buffer
2020-03-19 23:30:18ITERATION TestPtpComplexStreamOperations24000Hz24b32b4ch.test === 1584657018.4064174
2020-03-19 23:30:18=> TestPtpComplexStreamOperations24000Hz24b32b4ch.test
2020-03-19 23:30:19     => Verify SSP ports:
2020-03-19 23:30:19     => Generate playback file
2020-03-19 23:30:20     => Topology iteration 0
2020-03-19 23:30:20                 => Create pipelines:
2020-03-19 23:30:20                 => Build topology
2020-03-19 23:30:20                             => Build and connect components of Playback Pipeline (id: 1)
2020-03-19 23:30:20                             => Build and connect components of Capture Pipeline (id: 2)
2020-03-19 23:30:20                             => Build Playback Pipeline (id: 1)
2020-03-19 23:30:20                             => Build Capture Pipeline (id: 2)
2020-03-19 23:30:20                             => Connect pipelines
2020-03-19 23:30:20                             => Complete Playback Pipeline (id: 1)
2020-03-19 23:30:20                             => Complete Capture Pipeline (id: 2)
2020-03-19 23:30:20                 => Configure audio interfaces
2020-03-19 23:30:20                             => Interface type: SSP, port index: 0 
2020-03-19 23:30:20                 => Playback iteration 0
2020-03-19 23:30:20                             => Create playback streams (0)
2020-03-19 23:30:20                             => Create capture streams (0)
2020-03-19 23:30:20                             => Start playback and capture streams (0)
2020-03-19 23:30:26                             => Stop playback streams (0)
2020-03-19 23:30:26                 => Free components
2020-03-19 23:30:26     => Verify captured stream 0
2020-03-19 23:30:26                 Expression check failed:
                                    Iter 0, checking if time of inter recorded in interval 2, on channel 1.
                                    Expected:	1.02
                                    Got:		0.00
2020-03-19 23:30:26  

@singalsu singalsu deleted the testbench_load_process branch September 15, 2022 13:14
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3 participants