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SSP BLCK and MCLK early start - take3 #4288
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tools/topology/sof-tgl-nocodec.m4
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spurious change
set clks_control to (SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES | SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES) to enable MCLK/BCLK early start feature. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Enable the bclk clock control for SSP2. Note that this impacts existing GLK-based chromebooks as well as newer hardware. Signed-off-by: Brent Lu <brent.lu@intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
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@bardliao @lgirdwood @brentlu this was indeed a backwards-compatibility issue. We only want to use the _ES bits when the kernel makes use of the HW_PARAMS and HW_FREE stages, so I introduced an indirection with a new set of flags. See the difference here compared to the last version: I tested with an 'old' kernel and a 'new' one, in the first case the bclk/fsync start at the usual 4.2ms earlier than data (pipeline delay), and in the second case the bclk starts earlier. |
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Good finding and good fix |
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Sorry I am not quite confident about this, the merging of the Linux PR is a one of my suspects which introduces Xrun regression on TGLU_RVP_NOCODEC daily test. |
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@keyonjie please keep us updated. I dont think this side should cause an xrun on one platform only. |
what xrun and what issue @keyonjie? The tests show an IPC error |
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@keyonjie I've run tests with the latest kernel with and without this PR, I don't see any xrun on APL_NOCODEC (same results as CI). I will note btw that your TGL_NOCODEC topology does not use dynamic pipelines but this is configured for EHL: Something clearly misaligned. @ranj063 was this intentional? |
absolutely not. I seem to have missed the sof-tgl-nocodec case. But I've added tihs in my other PR to enable more dynamic pipeline topologies |
Ack @ranj063. there's also the TGL_NOCODEC_CI topology in development/CMakefiles.txt |
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@lgirdwood @plbossart if you check the FW etrace, you will find xrun reported and that's why the IPC error happen in dmesg. |
Can you paste the link ? Not sure which test ? |
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@keyonjie any updates here ? |
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let me start a daily-test coverage level test plan with this today, and come back with the result. |
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@plbossart @lgirdwood @bardliao @brentlu there are more than 10 TGLU_RVP_NOCODEC cases failed with this PR applied, according to the CI plan test result 4783. |
@keyonjie Do you know what 488520, 487496 , and 488008 registers are? |
These are SSP TFL/TNF registers, but these errors happen on each ssp_stop() both with and without the changes here. I think the problem is that in some cases SSP dai DMA will hit xrun more easily with the changes here applied. |
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the only timing change is the set config command moved from hw_params() to prepare() BTW, does the TGLU_RVP_NOCODEC means there is no codec connected to the SSP port? |
But the change is on kernel side and it is already merged. The only difference I can tell is that we enabled MCLK and BCLK early start feature in this PR. But I have no idea how will it cause XRUN.
Correct. |
So this PR is included in the test plan and cause XRUN? |
But I don't see those error in the PASS cases.
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@keyonjie I am afraid I will have to give up. The results show failures on SoundWire platforms as well, so I just can't trust the results of those tests. The results on TGL nocodec make no sense either, there's no explanation for xruns when the only change is to start the SSP earlier. And now there are conflicts? I've spent enough time on this PR, someone will have to take over. |
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I reserved a TGLU_RVP_NOCODEC device from CI pool and manually ran the check-playback-100times.sh test and no issue found. I just created a new PR to fix the conflict and will trigger a new CI test with that PR. |
This PR is the companion of kernel PR thesofproject/linux#2965
This builds on previous PRs from @bardliao (PR ##4219) and @brentlu (PR #4262)
We also build on previous work from @juimonen for the multi-ssp config where we send a DAI_CONFIG IPC in the hw_params and hw_free stages. Currently we send the same information in the two cases, so the firmware cannot take any action wrt. early clock enablement. Adding a flag is enough to provide the firmware with the information missing.
This is tagged as an ABI 3.18 change.
Results with a 50ms delay added in the kernel shows the bclock starting early and stopping late. The FSYNC starts with the data but that's explained (see commit messages).