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Merged
plbossart merged 11 commits into from
Jun 25, 2021
Merged

topology: align all cAVS nocodec topologies #4378

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ac19499
topology: CMakelists: group nocodec together
plbossart Jun 18, 2021
0cabc99
topology: CMakelist: disable DYNAMIC pipelines for nocodec topologies
plbossart Jun 24, 2021
7361acc
topology: sof-cnl-nocodec: use DMIC macros
plbossart Jun 18, 2021
8090978
topology: sof-cnl-nocodec: add macros for SSP cores
plbossart Jun 18, 2021
d8fb650
topology: sof-cnl-nocodec: use s32le
plbossart Jun 18, 2021
3a31e65
topology: sof-cnl-nocodec: make SSP clocks parameters
plbossart Jun 18, 2021
092d4bf
topology: sof-cnl-nocodec: change SSP index for APL
plbossart Jun 18, 2021
2a8e77d
topology: intel-generic-dmic: add macro for DMIC_CORE_ID
plbossart Jun 18, 2021
e0ddc31
topology: sof-cnl-nocodec: prepare for different multicore configurat…
plbossart Jun 18, 2021
94e8a61
topology: use same file for all cavs 1.8+ nocodec topologies
plbossart Jun 18, 2021
3e393d4
topology: use cAVS nocodec support for APL/GLK
plbossart Jun 18, 2021
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17 changes: 11 additions & 6 deletions tools/topology/topology1/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,6 @@ set(TPLGS
"sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0\;-DDYNAMIC=1"
"sof-hda-generic-idisp\;sof-hda-generic-idisp-2ch\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1"
"sof-hda-generic-idisp\;sof-hda-generic-idisp-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1"
"sof-apl-nocodec\;sof-apl-nocodec"
"sof-apl-keyword-detect\;sof-apl-keyword-detect"
"sof-bdw-codec\;sof-bdw-rt286\;-DCODEC=RT286"
"sof-bdw-codec\;sof-bdw-rt5640\;-DCODEC=RT5640"
Expand Down Expand Up @@ -78,8 +77,15 @@ set(TPLGS
"sof-glk-da7219\;sof-glk-da7219\;-DHEADPHONE=da7219"
"sof-glk-da7219\;sof-glk-cs42l42\;-DHEADPHONE=cs42l42"
"sof-glk-rt5682\;sof-glk-rt5682"
"sof-icl-nocodec\;sof-icl-nocodec\;-DPLATFORM=icl\;-DDYNAMIC=1"
"sof-icl-nocodec\;sof-jsl-nocodec\;-DPLATFORM=jsl\;-DDYNAMIC=1"
"sof-cavs-nocodec\;sof-apl-nocodec\;-DPLATFORM=bxt"
"sof-cavs-nocodec\;sof-glk-nocodec\;-DPLATFORM=bxt"
"sof-cavs-nocodec\;sof-cnl-nocodec\;-DPLATFORM=cnl"
"sof-cavs-nocodec\;sof-cml-nocodec\;-DPLATFORM=cml"
"sof-cavs-nocodec\;sof-icl-nocodec\;-DPLATFORM=icl"
"sof-cavs-nocodec\;sof-jsl-nocodec\;-DPLATFORM=jsl"
"sof-cavs-nocodec\;sof-tgl-nocodec\;-DPLATFORM=tgl"
"sof-cavs-nocodec\;sof-ehl-nocodec\;-DPLATFORM=ehl"
"sof-cavs-nocodec\;sof-adl-nocodec\;-DPLATFORM=adl"
"sof-icl-dmic-4ch\;sof-icl-dmic-4ch"
# sof-icl-r700 is kept for compatibility with CI and previous versions of the kernel.
"sof-icl-rt700\;sof-icl-rt700\;-DCHANNELS=4\;-DPLATFORM=icl\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4"
Expand Down Expand Up @@ -109,17 +115,16 @@ set(TPLGS
"sof-cml-rt5682-kwd\;sof-icl-rt5682-kwd\;-DPLATFORM=icl"
"sof-cml-demux-rt5682\;sof-cml-demux-rt5682\;-DPLATFORM=cml"
"sof-cml-demux-rt5682\;sof-whl-demux-rt5682\;-DPLATFORM=whl"
"sof-cnl-nocodec\;sof-cnl-nocodec\;-DDYNAMIC=1"
"sof-cml-rt5682-max98357a\;sof-cml-rt5682-max98357a\;-DPLATFORM=cml"
"sof-cml-demux-rt5682-max98357a\;sof-cml-demux-rt5682-max98357a\;-DPLATFORM=cml"
"sof-cml-rt1011-rt5682\;sof-cml-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=volume"
"sof-tgl-nocodec\;sof-tgl-nocodec"

"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-2ch\;-DCHANNELS=2\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-4ch\;-DCHANNELS=4\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711\;-DCHANNELS=0\;-DPLATFORM=adl"
"sof-tgl-nocodec\;sof-ehl-nocodec\;-DDYNAMIC=1"

"sof-ehl-rt5660\;sof-ehl-rt5660\;-DHDMI=1"
"sof-ehl-rt5660\;sof-ehl-rt5660-nohdmi"
"sof-imx8-nocodec\;sof-imx8-nocodec"
Expand Down
1 change: 1 addition & 0 deletions tools/topology/topology1/development/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ set(TPLGS
"sof-apl-src-50khz-pcm512x\;sof-apl-src-50khz-pcm512x"
"sof-cml-src-rt5682\;sof-cml-src-rt5682"
"sof-hda-asrc\;sof-hda-asrc-2ch\;-DCHANNELS=2"
"sof-apl-nocodec-ci\;sof-apl-nocodec-ci"
"sof-tgl-nocodec-ci\;sof-tgl-nocodec-ci"
"sof-cml-rt1011-rt5682-nokwd\;sof-cml-rt1011-rt5682-nokwd\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4"
"sof-cml-rt1011-rt5682-nokwd\;sof-cml-rt1011-rt5682-eq\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DHSEARPROC=eq-iir-eq-fir-volume\;-DHSMICPROC=eq-fir-volume\;-DSPKPROC=eq-iir-eq-fir-volume"
Expand Down
0 tools/topology/topology1/sof-apl-nocodec.m4 → ...pology1/development/sof-apl-nocodec-ci.m4
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File renamed without changes.
11 changes: 7 additions & 4 deletions tools/topology/topology1/platform/intel/intel-generic-dmic.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,9 @@ ifdef(`DMIC_DAI_LINK_48k_NAME',`',define(DMIC_DAI_LINK_48k_NAME, `dmic01'))
# define(DMIC_DAI_LINK_16k_NAME, `dmic16k')
ifdef(`DMIC_DAI_LINK_16k_NAME',`',define(DMIC_DAI_LINK_16k_NAME, `dmic16k'))

ifdef(`DMIC_48k_CORE_ID',`', define(DMIC_48k_CORE_ID, `0'))
ifdef(`DMIC_16k_CORE_ID',`', define(DMIC_16k_CORE_ID, `0'))

# Handle possible different channels count for PCM and DAI
ifdef(`DMIC_DAI_CHANNELS', `', `define(DMIC_DAI_CHANNELS, CHANNELS)')
ifdef(`DMIC_PCM_CHANNELS', `', `define(DMIC_PCM_CHANNELS, CHANNELS)')
Expand Down Expand Up @@ -79,7 +82,7 @@ define(`PGA_NAME', Dmic0)

PIPELINE_PCM_ADD(sof/pipe-DMICPROC-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC_PCM_48k_ID, DMIC_PCM_CHANNELS, s32le,
1000, 0, 0, 48000, 48000, 48000)
1000, 0, DMIC_48k_CORE_ID, 48000, 48000, 48000)

undefine(`PGA_NAME')
undefine(`PIPELINE_FILTER1')
Expand All @@ -94,7 +97,7 @@ define(`PGA_NAME', Dmic1)

PIPELINE_PCM_ADD(sof/pipe-DMIC16KPROC-capture-16khz.m4,
DMIC_PIPELINE_16k_ID, DMIC_PCM_16k_ID, DMIC16K_PCM_CHANNELS, s32le,
1000, 0, 0, 16000, 16000, 16000)
1000, 0, DMIC_16k_CORE_ID, 16000, 16000, 16000)

undefine(`PGA_NAME')
undefine(`PIPELINE_FILTER1')
Expand All @@ -116,14 +119,14 @@ dnl deadline, priority, core, time_domain)
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC, 0, DMIC_DAI_LINK_48k_NAME,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
1000, 0, DMIC_48k_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is DMIC 1 using 2 periods
# Buffers use s32le format, with 16 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_16k_ID, DMIC, 1, DMIC_DAI_LINK_16k_NAME,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_16k_ID), 2, s32le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
1000, 0, DMIC_16k_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
dnl PCM_CAPTURE_ADD(name, pipeline, capture)
Expand Down
289 changes: 289 additions & 0 deletions tools/topology/topology1/sof-cavs-nocodec.m4
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Original file line number Diff line number Diff line change
@@ -0,0 +1,289 @@
#
# Topology for generic Cannonlake board with no codec and digital mic array.
#

# Include topology builder
include(`utils.m4')
include(`dai.m4')
include(`ssp.m4')
include(`pipeline.m4')

# Include TLV library
include(`common/tlv.m4')

# Include Token library
include(`sof/tokens.m4')

# Include DSP configuration
include(`platform/intel/'PLATFORM`.m4')

# bxt has 2 cores but currently only one is enabled in the build
ifelse(PLATFORM, `bxt', `define(NCORES, 1)')
ifelse(PLATFORM, `cnl', `define(NCORES, 4)')
ifelse(PLATFORM, `cml', `define(NCORES, 4)')
ifelse(PLATFORM, `icl', `define(NCORES, 4)')
ifelse(PLATFORM, `jsl', `define(NCORES, 2)')
ifelse(PLATFORM, `tgl', `define(NCORES, 4)')
ifelse(PLATFORM, `ehl', `define(NCORES, 4)')
ifelse(PLATFORM, `adl', `define(NCORES, 4)')

define(CHANNELS, `4')

define(DMIC_PCM_48k_ID, `10')
define(DMIC_PCM_16k_ID, `11')

define(DMIC_PIPELINE_48k_ID, `20')
define(DMIC_PIPELINE_16k_ID, `21')

define(DMIC_DAI_LINK_48k_NAME, `NoCodec-3')
define(DMIC_DAI_LINK_16k_NAME, `NoCodec-4')

define(DMIC_DAI_LINK_48k_ID, `3')
define(DMIC_DAI_LINK_16k_ID, `4')

define(DMICPROC, `eq-iir-volume')
define(DMIC16KPROC, `eq-iir-volume')

define(DMICPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_48khz.m4')
define(DMIC16KPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_16khz.m4')

ifelse(NCORES, `4',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')

ifelse(NCORES, `2',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')

ifelse(NCORES, `1',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')

include(`platform/intel/intel-generic-dmic.m4')

ifelse(PLATFORM, `bxt',
`
define(SSP0_IDX, `0')
define(SSP1_IDX, `1')
define(SSP2_IDX, `5')
',
`
define(SSP0_IDX, `0')
define(SSP1_IDX, `1')
define(SSP2_IDX, `2')
')

#
# Define the pipelines
#
# PCM0 <---> volume <----> SSP0
# PCM1 <---> Volume <----> SSP1
# PCM2 <---> volume <----> SSP2
#

dnl PIPELINE_PCM_ADD(pipeline,
dnl pipe id, pcm, max channels, format,
dnl period, priority, core,
dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
dnl time_domain, sched_comp)

# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
# Set 1000us deadline on core 2 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
1000, 0, SSP0_CORE_ID,
48000, 48000, 48000)

# Volume switch capture pipeline 2 on PCM 0 using max 2 channels of s32le.
# Set 1000us deadline on core 2 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
2, 0, 2, s32le,
1000, 0, SSP0_CORE_ID,
48000, 48000, 48000)

# Low Latency playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# Set 1000us deadline on core 1 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
3, 1, 2, s32le,
1000, 0, SSP1_CORE_ID,
48000, 48000, 48000)

# Volume switch capture pipeline 4 on PCM 1 using max 2 channels of s32le.
# Set 1000us deadline on core 1 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
4, 1, 2, s32le,
1000, 0, SSP1_CORE_ID,
48000, 48000, 48000)

# Low Latency playback pipeline 5 on PCM 2 using max 2 channels of s32le.
# Set 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
5, 2, 2, s32le,
1000, 0, SSP2_CORE_ID,
48000, 48000, 48000)

# Volume switch capture pipeline 6 on PCM 2 using max 2 channels of s32le.
# Set 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
6, 2, 2, s32le,
1000, 0, SSP2_CORE_ID,
48000, 48000, 48000)

#
# DAIs configuration
#

dnl DAI_ADD(pipeline,
dnl pipe id, dai type, dai_index, dai_be,
dnl buffer, periods, format,
dnl deadline, priority, core, time_domain)

# playback DAI is SSP0 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, SSP0_IDX, NoCodec-0,
PIPELINE_SOURCE_1, 2, s32le,
1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is SSP0 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, SSP0_IDX, NoCodec-0,
PIPELINE_SINK_2, 2, s32le,
1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# playback DAI is SSP1 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
3, SSP, SSP1_IDX, NoCodec-1,
PIPELINE_SOURCE_3, 2, s32le,
1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is SSP1 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
4, SSP, SSP1_IDX, NoCodec-1,
PIPELINE_SINK_4, 2, s32le,
1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# playback DAI is SSP2 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
5, SSP, SSP2_IDX, NoCodec-2,
PIPELINE_SOURCE_5, 2, s32le,
1000, 0, SSP2_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is SSP2 using 2 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
6, SSP, SSP2_IDX, NoCodec-2,
PIPELINE_SINK_6, 2, s32le,
1000, 0, SSP2_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
PCM_DUPLEX_ADD(`Port'SSP0_IDX, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
PCM_DUPLEX_ADD(`Port'SSP1_IDX, 1, PIPELINE_PCM_3, PIPELINE_PCM_4)
PCM_DUPLEX_ADD(`Port'SSP2_IDX, 2, PIPELINE_PCM_5, PIPELINE_PCM_6)

#
# BE configurations - overrides config in ACPI if present
#

ifelse(PLATFORM, `bxt', `define(ROOT_CLK, 19_2)')
ifelse(PLATFORM, `cnl', `define(ROOT_CLK, 24)')
ifelse(PLATFORM, `cml', `define(ROOT_CLK, 24)')
ifelse(PLATFORM, `icl', `define(ROOT_CLK, 38_4)')
ifelse(PLATFORM, `jsl', `define(ROOT_CLK, 38_4)')
ifelse(PLATFORM, `tgl', `define(ROOT_CLK, 38_4)')
ifelse(PLATFORM, `ehl', `define(ROOT_CLK, 38_4)')
ifelse(PLATFORM, `adl', `define(ROOT_CLK, 38_4)')

ifelse(ROOT_CLK, `19_2',
`
DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
SSP_CLOCK(bclk, 3072000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks)
SSP_CONFIG_DATA(SSP, SSP0_IDX, 32, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
SSP_CLOCK(bclk, 3072000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
SSP_CONFIG_DATA(SSP, SSP1_IDX, 32, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
SSP_CLOCK(bclk, 3072000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
SSP_CONFIG_DATA(SSP, SSP2_IDX, 32, 0, SSP_QUIRK_LBM)))
')

ifelse(ROOT_CLK, `24',
`
DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
dnl SSP_CONFIG(format, mclk, bclk, fsync, tdm, ssp_config_data)
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
SSP_CLOCK(bclk, 4800000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks)
SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
SSP_CLOCK(bclk, 4800000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
SSP_CLOCK(bclk, 4800000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM)))
')

ifelse(ROOT_CLK, `38_4',
`
DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
SSP_CLOCK(bclk, 2400000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
SSP_CLOCK(bclk, 2400000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM)))

DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
SSP_CLOCK(bclk, 2400000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM)))
')
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