Backport bclk clock control to JSL branch #4644
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brentlu
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a team,
dbaluta,
lbetlej,
lgirdwood,
mmaka1,
plbossart and
ranj063
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Not sure we can merge to the jsl-004 branch or need to create an new one like jsl-004-hot-fix-1 ? |
brentlu
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rebase due to branch change |
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@brentlu I would recommend creating jsl-004-hot-fix-1 branch. I assume that you will maintain and validate the hot fix branch? |
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@mwasko yes, we work with ODM to validate the FW and TPLG for Chromebooks. |
When a DAI_CONFIG IPC is sent from the driver for a particular DAI type and index, all DAI components that match the type and index are configured. When all components are set up during topology loading, this isn't really much of a problem as all DAI_CONFIG IPCs will be sent at that time as well ie there is no active playback/capture. But with dynamic pipeline loading, the playback and capture DAIs will be individually configured whenever the respective pipeline is started. This will end up with errors both when configuring the SSP and when configuring the DAI comp itself. So, ignore the request to configure the SSP and the DAI comp that is already active so that the other DAI comp can be configured successfully when its pipeline is set up. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
The DAI_CONFIG IPC is currently used both for hw_params and hw_free. For some DAIs, there are hacky ways with e.g. invalid DMA channels to indicate a hw_free. Rather than adding a new IPC for hw_params and hw_free, let's add a flag that indicates if the DAI_CONFIG is really applied during a hw_params or hw_free stage. This is tagged as a ABI 3.19 change. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Add two clks_control bits. MCLK and/or BCLK will start during hw_params and stop during hw_free if the corresponding bit is set. This is tagged as a ABI 3.19 change. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Some codecs need the SSP bit clock to start before data is provided, and conversely the bit clock to remain active until the hw_free stage. For backwards-compatibility with older kernels, the SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES and SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES bitfields are used to set an internal state in the ssp->clk_active field. This helps deals with the case where a topology sets these bits but the older kernel does not make use of the modified IPC. While we are at it, add clearer info traces for SSP configurations. Note that the FSYNC only starts when DMA transfers are enabled in the .trigger stage. This is by-design, the FSYNC will only start if the FIFO is not empty. During the prepare stages the DMA transfers are not enabled so the FIFOs are empty. To enable the FSYNC at an earlier stage, we would need a major surgery in the SOF architecture, or we would need to start zero-based DMA transfers. Co-developed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
The current code does not follow recommended programming sequences: TSRE and RSRE should be set before SSE and conversely cleared before SSE. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Increase the API level to 3.18 so host will start sending dai_config IPCs in prepare/hw_free for mclk/bclk control. Signed-off-by: Brent Lu <brent.lu@intel.com>
The m4 ifelse check on macro parameters is not working as expected. If optional parameters are not passed, an empty string is written to output conf file, instead of the "0" string specified in the ifelse statement. This has not caused functional errors as the empty string has been interpreted as zero. Fix the logic despite this so that this is not copied to other macros. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Add all same tokens to SSP_CONFIG_DATA that we have in SSP_MULTI_CONFIG_DATA. Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Define the SSP_CC_MCLK/BCLK_ES bit to be used in SSP_CONFIG_DATA macro to enable mclk/bclk on hw_params and disable malk/bclk on hw_free. Signed-off-by: Brent Lu <brent.lu@intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Signed-off-by: Brent Lu <brent.lu@intel.com>
Add support for cs42l42 with max98360a running on JSL boards. The cs42l42 needs to enable bclk earlier in prepare stage and disable bclk at hw_free statge so we add the SSP_CC_BCLK_ES flag for it. Signed-off-by: Brent Lu <brent.lu@intel.com>
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Backport the PR to JSL branch to support cs42l42 headphone codec on JSL Chromebooks.
#4391