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@kuanhsuncheng kuanhsuncheng commented Aug 25, 2021

Hi,

I am Allen Cheng (KuanHsun Cheng) from Taiwan,

Currently working for Mediatek as a chromebook project developer.

The other co-worker is YC Hung (My colleague in Mediatek).

There are some drivers and platform codes we have been verified in mt8195 prototype device (chrombook).

Also all of those commits have been reviewed by Google engineers.

We want to add mtk mt8195 platform support to sof project.

Please review those commits.

If there is any questions, please let us know.

Thanks.

mtk mt8195 :
Cadence HiFi-4 DSP, single core, currently we support 4 dais , 4 dmas and 48k 16 bits

@sofci
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sofci commented Aug 25, 2021

Can one of the admins verify this patch?

reply test this please to run this test once

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Can one of the admins verify this patch?

@kuanhsuncheng kuanhsuncheng force-pushed the mt8195-dev branch 2 times, most recently from ba420d2 to 56e7da3 Compare August 25, 2021 08:57
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Can you please add a small description of the target: what DSP it has (from code review I realized is Hifi4), how many cores, how many DAIs, DMAs, what rates are supported, formats, etc. ?
There is a lot of code and I believe it would help reviewing.
Thanks!

@marc-hb marc-hb requested a review from cujomalainey August 25, 2021 11:47
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It's nice to try to split this giant PR into 6 different commits, however the way the split is performed right now is not OK: each commit is simply adding a subset of files. This is likely breaking bisectability.

Commits must represent logical changes https://wiki.openstack.org/wiki/GitCommitMessages#Structural_split_of_changes

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dbaluta commented Aug 25, 2021

@kuanhsuncheng That's good news! Do you also have a Linux kernel change for your device?

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@kuanhsuncheng That's good news! Do you also have a Linux kernel change for your device?

Hi, we are working on this. it should upstream this week.

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dbaluta commented Aug 25, 2021

Hi, we are working on this. it should upstream this week.

Great thanks you guys! AFAICT your non-DSP cores are ARM A cores, right? Do you also have some GCC toolchain patches for compiling the firmware OR are you just using the proprietary xt-cc stuff?

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Hi Allen,

Thanks for the PR, I've detailed some high level items that need to be done throughout the PR. Best to go through and make sure the review changes are made to all files (except the Cadence files).

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Hi sirs,

I update some code following above comments.

Anything inappropriate in those commits, please let me know.

I'd appreciate your comments.

Thanks.

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Thanks for addressing the comments!

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@lyakh Hi

I have done some modifications.

mono = (bool)memif->data->mono_invert ^ (channel == 1);

should be more close to original.

also remove ret variable.

thanks for your comments.

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I think we are almost good to merge, just some minor review questions that can be answered. Please mark them as resolved so we can track.

Comment on lines 17 to 19
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any update here ? Changing these later is difficult, if these are DAI HW settings only then we are good.

Add irq, ipc and timer drivers for mtk mt8195

About mt8195:
Two domains of IRQ:
IRQ_EXT_DOMAIN0 and IRQ_EXT_DOMAIN1

IRQ num: 25 interrupts
IPC: use mbx0 and mbx1 to transfer ipc msg

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add memory layout and register address for mtk mt8195

mt8195:
Cache
   I-Cache: 32KB, 4-way Associativity
   D-Cache: 128KB, 4-way Associativity
External Memory
    DRAM: DSP can access DRAM which shared with CPU
    L2TCM: 256KB DSP SRAM POOL

Currently, use
phy addr:0x60000000, size:0x1000000
dma phy addr: 0x61000000, size: 0x0100000

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add support for platform drivers :
idc, irq, timer, clk dma.

Add mtk mt8195 platform initialization.

1. MT8195 includes one Cadence HiFi-4  DSP,
which support for four 32x32-bit MACs,
some support for 72-bit accumulators,
limited ability to support eight 32x16-bit MACs,
a fourth VLIW slot and the ability to issue two 64-bit loads per cycle.
2. 25 interrupts
3. Clock Rate: DSP can operate at
720 MHz (0P75 V)/540 MHz (0P65 V)/370 MHz (0P6 V)/220 MHz (0P55 V)
4. DRAM: it can access data on DRAM by DMA or by CPU directly (through Cache).
5. 32x32-bit MACs
6. Supports SPM(System Power Manager) to control power sequence

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add mt8195 driver and platform compile support.

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add afe driver for memif/sinegen.
Add afe-dai.c/afe-drv.c/afe-memif.c for afe common driver

AFE : Audio Front End

The audio front-end essentially consists of voice and audio data paths.

frontend (memif) :
  memory interface,
  UL (uplink for capture),
  DL(downlink for playback)
backend:
  TDM In,
  TMD out,
  DMIC,
  GASRC, etc
interconn:
  inter-connection,
  connect frontends
  backends as DSP path

Note:
TEST_SGEN macro define is just for test

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add memif data for afe
Add common and regs header for afe
Add afe platform for mt8195 audio/dsp

AFE: the abbreviation for Audio Front End

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
The AFE is a audio hw interface on the mt8195 platform.
This commit brings the compile support for the AFE.

The audio front-end essentially consists of voice and audio data paths

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add mt8195 pipelines and components

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add sof-mt8195-mt6359-rt1019-rt5682.m4 for mt8195

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add afe.m4 for afe related define

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add afe tokens for mt8195

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add afe config for mt8195

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Add sof-mt8195-mt6359-rt1019-rt5682 topology

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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@lgirdwood

Hi Sir,

about
https://github.com/thesofproject/sof/pull/4679#discussion_r702953545

After discuss with YC, we prefix dai_ in below those parameters.

uint32_t channels;
uint32_t rate;
uint32_t format;

The same change will sync to the dai mtk header file in kernel sof (dai-mediatek.h).

thanks for your comments.

@lgirdwood lgirdwood added the ABI ABI change involved label Sep 7, 2021
@lgirdwood lgirdwood added this to the v1.9 milestone Sep 7, 2021
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dbaluta commented Sep 7, 2021

@kuanhsuncheng this is good enough for me to be merged. We can adjust the code later if there are any issues.

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CI failure on TGL report unrelated to this PR.

@lgirdwood lgirdwood merged commit 7eda2d5 into thesofproject:main Sep 7, 2021
@kuanhsuncheng kuanhsuncheng deleted the mt8195-dev branch September 7, 2021 12:35
@kuanhsuncheng kuanhsuncheng restored the mt8195-dev branch September 7, 2021 12:35
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