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topology: align core target for dmic16k to dmic01 #6916

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topology: align core target for dmic16k to dmic01 #6916

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9 changes: 6 additions & 3 deletions tools/topology/topology1/platform/intel/intel-generic-dmic-kwd.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,9 @@ ifdef(`DMIC_PIPELINE_48k_CORE_ID',`',define(DMIC_PIPELINE_48k_CORE_ID, 0))
# define(DMIC_DAI_LINK_16k_NAME, `dmic16k')
ifdef(`DMIC_DAI_LINK_16k_NAME',`',define(DMIC_DAI_LINK_16k_NAME, `dmic16k'))

dnl Align the core target for dmic16k to dmic01 (48k)
define(DMIC_PIPELINE_16k_CORE_ID, DMIC_PIPELINE_48k_CORE_ID)
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@plbossart plbossart Jan 5, 2023

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well if you want to align, then the 48k pipeline needs to use core 0.

To optimize power consumption the dmic16k + WoV need to be on core0.

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@johnylin76 johnylin76 Jan 5, 2023

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Thanks for the info @plbossart
Is it because core0 is reserved for WoV as default (which might be in different power state from other cores while suspended)?

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@plbossart plbossart Jan 5, 2023

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core0 is on by default, and then other cores are turned on as needed which increases power consumption. So the recommended practice since forever is to place everything that needs to run in low-power use cases on core0, and use cores1..3 for processing, e.g. speaker protection and noise suppression on capture.

That said, it may be impossible at this point to move all the DMIC48k stuff to core0 if that core0 is already oversubscribed. that would mean different possible alternatives:
a) using your solution with an understanding that there's a power impact for WoV.
b) fixing the root cause and making sure the two paths can be used on different pipelines.

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@johnylin76 johnylin76 Jan 6, 2023

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So theoretically it should be fine for DMIC48K and DMIC16K running on the different core?

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@plbossart plbossart Jan 6, 2023

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I think it's expected in terms of architecture that DMIC16k stuff is on core0 and other DMIC48k stuff is on other cores, but between architecture and implementation we may have a gap. I don't know if the panic you're seeing is by design or really a bug.


# DMICPROC is set by makefile, available type: passthrough/eq-iir-volume
ifdef(`DMICPROC', `', `define(DMICPROC, passthrough)')

Expand Down Expand Up @@ -89,7 +92,7 @@ undefine(`DMICPROC')
# Schedule 20000us deadline with priority 0 on core 0
PIPELINE_PCM_DAI_ADD(sof/pipe-KFBM_TYPE-capture.m4,
DMIC_PIPELINE_16k_ID, DMIC_PCM_16k_ID, 2, s32le,
KWD_PIPE_SCH_DEADLINE_US, 0, 0, DMIC, 1, s32le, 3,
KWD_PIPE_SCH_DEADLINE_US, 0, DMIC_PIPELINE_16k_CORE_ID, DMIC, 1, s32le, 3,
16000, 16000, 16000)


Expand All @@ -115,7 +118,7 @@ DAI_ADD(sof/pipe-dai-capture.m4,
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_16k_ID, DMIC, 1, DMIC_DAI_LINK_16k_NAME,
`PIPELINE_SINK_'DMIC_PIPELINE_16k_ID, 3, s32le,
KWD_PIPE_SCH_DEADLINE_US, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
KWD_PIPE_SCH_DEADLINE_US, 0, DMIC_PIPELINE_16k_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)

dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
dnl PCM_CAPTURE_ADD(name, pipeline, capture)
Expand All @@ -129,7 +132,7 @@ dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
dnl time_domain, sched_comp, dynamic)
PIPELINE_PCM_ADD(sof/pipe-DETECTOR_TYPE.m4,
DMIC_PIPELINE_KWD_ID, DMIC_PCM_16k_ID, 2, s24le,
KWD_PIPE_SCH_DEADLINE_US, 1, 0,
KWD_PIPE_SCH_DEADLINE_US, 1, DMIC_PIPELINE_16k_CORE_ID,
16000, 16000, 16000,
SCHEDULE_TIME_DOMAIN_TIMER,
`PIPELINE_SCHED_COMP_'DMIC_PIPELINE_16k_ID)
Expand Down