[cavs2.5-001-drop-stable] intel: ssp: TX and RX FIFO drain fixes #7716
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Use the actual TX fifo load level to calculate the timeout to wait until the TX fifo is empty. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The receive FIFO needs to be drained in a different way depending when it is done. - before start If the RX FIFO is in overflow state then we must read all the entries out to empty it (it was after all full). - before stop The DMA might be already running to read out data. Check the FIFO level change in one sample time which gives us the needed information to decide to wait for another loop for the DMA burst to finish, wait for the DMA to start it's burst (DMA request was asserted) or drain the FIFO directly. No need to drain the RX fifo at probe time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
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created against wrong branch.... |
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Hi,
both the TX and RX FIFO drain handling have issues currently, both fixed by this PR.
On TX side we regularly see:
The reason is that the 'calculated' timeout is incorrect for low sampling rates.
On RX side the FIFO draining needs to follow different strategies depending on when the draining is done to avoid starting and stopping issues.
This PR can replace #7711, so far it is holding up to the local stress tests.