west.yml: update zephyr to f29377a12cb5 (Aug 26th) #9407
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Total of 845 commits. Changes include: 746ddccf54ca intel_adsp: debug_window: Add slot type for debug-stream transport 8a4b3a4b618a xtensa: include xtensa-types.h for xt-clang e0be5801cd70 drivers: dai: esai: don't reset ESAI on init 32cf0e0f9f2c intel_adsp: ace: Fix undefined reference 8fb592dfff6c soc: intel_adsp: DCACHE_LINE_SIZE was not defined 85758444f7d8 intel_adsp: clk: Configure correct cardinal clock divider for PTL 784bc06e7ecd soc: intel_adsp: ace: set xtensa ccount per platform b0185189ad7e xtensa: mmu: fix page table initialization f2840910731d xtensa: core: Remove constant branch Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
kv2019i
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dbaluta,
lbetlej,
lgirdwood,
mmaka1 and
plbossart
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ujfalusi
approved these changes
Aug 27, 2024
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I guess, the LNL is what it is?
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Superceded by #9319 |
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Total of 845 commits.
Changes include:
746ddccf54ca intel_adsp: debug_window: Add slot type for debug-stream
transport
8a4b3a4b618a xtensa: include xtensa-types.h for xt-clang e0be5801cd70 drivers: dai: esai: don't reset ESAI on init 32cf0e0f9f2c intel_adsp: ace: Fix undefined reference 8fb592dfff6c soc: intel_adsp: DCACHE_LINE_SIZE was not defined 85758444f7d8 intel_adsp: clk: Configure correct cardinal clock divider
for PTL
784bc06e7ecd soc: intel_adsp: ace: set xtensa ccount per platform b0185189ad7e xtensa: mmu: fix page table initialization f2840910731d xtensa: core: Remove constant branch