Input clock for ICS307 is too high in the bringup design

[zephray]

In the page 8 of ICS307 datasheet, it mentioned the maximum clock input frequency is 50MHz, however, currently it looks like it is connected directly to the 100MHz clock source:

panologic/bringup/rtl/idt_clkgen.v

Line 60 in fd46889

assign idt_iclk = osc_clk;

Yes, I have tried, it actually works, but I guess a better practice would be feeding a divided clock, like 50MHz or 25MHz.

[cb88]

It's probably fine, the chip's actual max input clock frequency is 300Mhz, it was probably only verified with 10-50Mhz crystals however in that configuration. Also it isn't doing anything particularly special in that startup mode but buffering a clock signal and dividing it by half on the other outputs.

Why feed a divided clock... to a chip whose entire purpose, and then some, is to be a clock divider... not much sense in that.

[zephray]

Where did you read the the actual max input freq is 300MHz? I see the max output is 200M, but max input is 27M for crystal and 50M for clock. The reason for feeding a divided clock is simple, it is only guranteed to work up to 50M, by feeding in 100M you are overclocking the chip. I don't understand why it doesn't make sense to stay within the specification. Yeah, it works just fine under 100M, and no one really should care about that if it works. I am just pointing out.

[cb88]

It's in the datasheet mentioned in the AC characteristics. I guess it depends on if it is a -02 or a -03 chip... I just checked and the datasheet's do have different specs for them both.

[zephray]

I am looking at the datasheet linked from the readme page,

[zephray]

Just confirmed that my Pano Logic G1 comes with a -02 chip, ICS307M-02LF, so it should be 50MHz instead of 300MHz, at least on my unit. I am not sure about others.

[tomverbeure]

Ok. I'll add the divider. It's a simple enough change.

Tom