Issues with <= glyph

[drom]

In SystemVerilog language there are two usages for operator <=

1. traditional less-or-equal
2. non-blocking assignment http://www.asic-world.com/tidbits/blocking.html more like left fat arrow.

Less-or-equal glyph looks wired as fat-arrow. Is any way to disable particular glyph? or switch depend on context?
I am using Atom

[tonsky]

No way do disable single ligature unfortunately

[tonsky]

Will be in v6 as cv20-cv22