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cpu-architecture

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Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

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Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
  • Updated Jul 21, 2025
  • SystemVerilog

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