A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Nov 14, 2025 - SystemVerilog
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digital-design
Here are 52 public repositories matching this topic...
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
simulation verification vip systemverilog questasim uvm verification-methodologies testbench semiconductor digital-design uvm-verification ahb2apb
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Mar 3, 2024 - SystemVerilog
An open source, parameterized SystemVerilog digital hardware IP library
asic fpga hardware ip verilog systemverilog hardware-designs hardware-libraries hdl digital-design asic-library fpga-library
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May 26, 2024 - SystemVerilog
北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇
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Aug 31, 2024 - SystemVerilog
Minimalistic RV32I RISC-V Processor in System Verilog
fpga processor simulations systemverilog computer-architecture instruction-set-architecture risc-v digital-design rv32i
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Sep 19, 2023 - SystemVerilog
SystemVerilog examples for a digital design course
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Mar 30, 2021 - SystemVerilog
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
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Jul 6, 2021 - SystemVerilog
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
fpga processor systemverilog processors digital-design quartus-prime quartus de10-lite processor-design jakujobi
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Dec 8, 2023 - SystemVerilog
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
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Jun 7, 2020 - SystemVerilog
Term project for CS223 Digital - Design course.
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Nov 2, 2021 - SystemVerilog
UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
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Nov 1, 2025 - SystemVerilog
MIPS written in System Verilog
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Oct 17, 2017 - SystemVerilog
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
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May 5, 2022 - SystemVerilog
A simple Floating-Point arithmetic unit - implemented in SystemVerilog
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Mar 11, 2024 - SystemVerilog
ucrv32 is a simple educational RV32I microcontroller featuring a 5-stage pipeline architecture. Written in SystemVerilog and equipped with simulation support via Verilator, it offers a practical platform for learning digital design and computer architecture concepts.
microcontroller pipeline educational systemverilog computer-architecture risc-v digital-design rv32i verilator
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Mar 31, 2025 - SystemVerilog
A collection of systemverilog designs implemented on AMD Vivado tool
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Nov 27, 2025 - SystemVerilog
Cuarto laboratorio del curso de Taller de Diseño Digital. La idea es generar un código compilable para una FPGA con la que se pueda simular el funcionamiento de máquina de café utilizando el lenguaje de programación SystemVerilog.
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May 5, 2022 - SystemVerilog
A single cycle processor implementing a subset of the ARMv7 ISA.
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Sep 11, 2018 - SystemVerilog
This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.
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Jun 18, 2024 - SystemVerilog
Compare the speeds of the Carry ripple adder and Carry-lookahead adder
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Oct 17, 2017 - SystemVerilog
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