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ece
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A simple UART Transmitter built in Verilog using FSM and tested with Icarus Verilog + GTKWave.
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Jul 13, 2025 - Verilog
Files regarding synthesis and floorplanning of a RISC V proccessor, using Cadence Genus and Innovus. Project is part of class Digital VLSI-ASIC Design, 9th semester, ECE Aristotle University.
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Jan 26, 2025 - Verilog
A Verilog HDL project for an Elevator Control System, complete with a Python Tkinter GUI for real-time simulation. 🚀
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Oct 26, 2025 - Verilog
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