This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.
ram memory advanced verilog test-bench vlsi-design nptel-solutions memory-design btech-project mtechprojects
-
Updated
Aug 3, 2025 - Verilog