A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
-
Updated
Sep 3, 2025 - JavaScript