Fix multicore arcsync reset

arch/arc/Kconfig

@@ -32,6 +32,7 @@ config ARC
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
 	select HAVE_DEBUG_STACKOVERFLOW
 	select HAVE_DEBUG_KMEMLEAK
+	select HAVE_DMA_CONTIGUOUS
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_IOREMAP_PROT
 	select HAVE_KERNEL_GZIP

arch/arc/boot/dts/haps_hs_npp.dts

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+/include/ "skeleton_hs.dtsi"
+
+/ {
+	model = "snps,haps_npp";
+	compatible = "snps,haps_npp";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&core_intc>;
+
+	memory {
+		device_type = "memory";
+		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
+		reg = <0x0 0xB0000000 0x0 0x10000000	/* 1 GB low mem */
+		       0x1 0x00000000 0x0 0x40000000>;	/* 1 GB highmem */
+	};
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xd5008000,9600n8 console=ttyS0,9600n8 debug print-fatal-signals=1 drm.debug=0";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	fpga {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* only perip space at end of low mem accessible
+			  bus addr,  parent bus addr, size    */
+		ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <4000000>;
+		};
+
+		core_intc: interrupt-controller {
+			compatible = "snps,archs-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		uart0: serial@d50080000 {
+			compatible = "ns16550a";
+			reg = <0xd5008000 0x1000>;
+			interrupts = <18>;
+			clock-frequency = <4000000>;
+			baud = <9600>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test = <1>;
+		};
+	};
+
+	npu_cfg0: npu_cfg@d3000000 {
+		reg = <0x0 0xd3000000 0x0 0xF4000>;
+		snps,npu-slice-num = <1>;
+	};
+
+	arcsync0: arcsync@d4000000 {
+		compatible = "snps,arcsync";
+		reg = <0x0 0xd4000000 0x0 0x1000000>;
+		interrupts = <24>;
+	};
+
+	snps_accel@0 {
+		compatible = "snps,accel", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x0000000 0x0 0x80000000>;
+		ranges = <0x0 0x0 0x0 0x80000000>;
+
+		remoteproc_npx0: remoteproc_npx@0x8000000 {
+			compatible = "snps,npx-rproc";
+			reg = <0x8000000 0x2000000>;
+			firmware-name = "npx-app.elf";
+			snps,npu-cfg = <&npu_cfg0>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			snps,arcsync-core-id = <0x1>;
+			snps,arcsync-cluster-id = <0x0>;
+			snps,auto-boot;
+		};
+
+		app_npx0: app_npx@0 {
+			compatible = "snps,accel-app";
+			reg = <0x20000000 0x10000000>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			interrupts = <24>;
+		};
+	};
+};

arch/arc/boot/dts/haps_hs_npx6_8k_vpx.dts

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+/include/ "skeleton_hs.dtsi"
+
+/ {
+	model = "snps,haps_npp";
+	compatible = "snps,haps_npp";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&core_intc>;
+
+	memory {
+		device_type = "memory";
+		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
+		reg = <0x0 0xB0000000 0x0 0x10000000	/* 1 GB low mem */
+		       0x1 0x00000000 0x0 0x40000000>;	/* 1 GB highmem */
+	};
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xd5008000,19200n8 console=ttyS0,19200n8 debug print-fatal-signals=1 drm.debug=0";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		reserved: buffer@bc000000 {
+			compatible = "shared-dma-pool";
+			reusable;
+			reg = <0x0 0xBC000000 0x0 0x04000000>;
+			linux,cma-default;
+		};
+	};
+
+	fpga {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* only perip space at end of low mem accessible
+			  bus addr,  parent bus addr, size    */
+		ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <4000000>;
+		};
+
+		core_intc: interrupt-controller {
+			compatible = "snps,archs-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		uart0: serial@d50080000 {
+			compatible = "ns16550a";
+			reg = <0xd5008000 0x1000>;
+			interrupts = <18>;
+			clock-frequency = <4000000>;
+			baud = <19200>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test = <1>;
+		};
+	};
+
+	npu_cfg0: npu_cfg@d3000000 {
+		reg = <0x0 0xd3000000 0x0 0xF4000>;
+		snps,npu-slice-num = <2>;
+	};
+
+	arcsync0: arcsync@d4000000 {
+		compatible = "snps,arcsync";
+		reg = <0x0 0xd4000000 0x0 0x1000000>;
+		snps,host-cluster-id = <0x2>;
+		interrupts = <24>;
+	};
+
+	snps_accel@0 {
+		compatible = "snps,accel", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x0000000 0x0 0x80000000>;
+		ranges = <0x0 0x0 0x0 0x80000000>;
+
+		remoteproc_vpx0: remoteproc_vpx@0x18000000 {
+			compatible = "snps,vpx-rproc";
+			reg = <0x18000000 0x01000000>;
+			firmware-name = "Deployment_vpx.elf";
+			snps,arcsync-ctrl = <&arcsync0>;
+			snps,arcsync-core-id = <0x0>;
+			snps,arcsync-cluster-id = <0x1>;
+			snps,auto-boot;
+		};
+
+		remoteproc_npx0: remoteproc_npx@0x5000000 {
+			compatible = "snps,npx-rproc";
+			reg = <0x20000000 0x2000000>;
+			firmware-name = "Deployment_l2.elf";
+			snps,npu-cfg = <&npu_cfg0>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			snps,arcsync-core-id = <0x0>;
+			snps,arcsync-cluster-id = <0x0>;
+			snps,auto-boot;
+		};
+
+		remoteproc_npx1: remoteproc_npx@0x8000000 {
+			compatible = "snps,npx-rproc";
+			reg = <0x10000000 0x2000000>;
+			firmware-name = "Deployment_l1.elf";
+			snps,arcsync-ctrl = <&arcsync0>;
+			snps,arcsync-core-id = <0x1>;
+			snps,arcsync-cluster-id = <0x0>;
+			snps,auto-boot;
+		};
+
+		app_npx2: app_npx@2 {
+			compatible = "snps,accel-app";
+			reg = <0x30000000 0x10000000>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			interrupts = <24>;
+		};
+	};
+};

arch/arc/boot/dts/zebu_hs_npp.dts

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+/include/ "skeleton_hs.dtsi"
+
+/ {
+	model = "snps,zebu_hs";
+	compatible = "snps,zebu_hs";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&core_intc>;
+
+	memory {
+		device_type = "memory";
+		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
+		reg = <0x0 0xB0000000 0x0 0x10000000	/* 1 GB low mem */
+		       0x1 0x00000000 0x0 0x40000000>;	/* 1 GB highmem */
+	};
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xd5008000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1 drm.debug=0";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	fpga {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* only perip space at end of low mem accessible
+			  bus addr,  parent bus addr, size    */
+		ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <1388000>;
+		};
+
+		core_intc: interrupt-controller {
+			compatible = "snps,archs-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		uart0: serial@d50080000 {
+			compatible = "ns16550a";
+			reg = <0xd5008000 0x1000>;
+			interrupts = <18>;
+			clock-frequency = <30000000>;
+			baud = <115200>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test = <1>;
+		};
+	};
+
+	npu_cfg0: npu_cfg@d3000000 {
+		reg = <0x0 0xd3000000 0x0 0xF4000>;
+		snps,npu-slice-num = <2>;
+	};
+
+	arcsync0: arcsync@d4000000 {
+		compatible = "snps,arcsync";
+		reg = <0x0 0xd4000000 0x0 0x1000000>;
+		interrupts = <24>;
+	};
+
+	snps_accel@0 {
+		compatible = "snps,accel", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x0000000 0x0 0x80000000>;
+		ranges = <0x0 0x0 0x0 0x80000000>;
+
+		remoteproc_npx0: remoteproc_npx@0x8000000 {
+			compatible = "snps,npx-rproc";
+			reg = <0x8000000 0x2000000>;
+			firmware-name = "npx-app.elf";
+			snps,npu-cfg = <&npu_cfg0>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			snps,arcsync-core-id = <0x1>;
+			snps,arcsync-cluster-id = <0x0>;
+			snps,auto-boot;
+		};
+
+		app_npx0: app_npx@0 {
+			compatible = "snps,accel-app";
+			reg = <0x20000000 0x10000000>;
+			snps,arcsync-ctrl = <&arcsync0>;
+			interrupts = <24>;
+		};
+	};
+};