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ALU
ALU
 
 
Datapath
Datapath
 
 
MAIN_PHASE1
MAIN_PHASE1
 
 
Testbenches
Testbenches
 
 
db
db
 
 
greybox_tmp
greybox_tmp
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
simulation/modelsim
simulation/modelsim
 
 
Bus.bdf
Bus.bdf
 
 
Bus.bsf
Bus.bsf
 
 
Bus.v
Bus.v
 
 
Bus.v.bak
Bus.v.bak
 
 
CpuDesign.bdf
CpuDesign.bdf
 
 
CpuDesign.qsf
CpuDesign.qsf
 
 
CpuDesign.qws
CpuDesign.qws
 
 
CpuDesignLab.qpf
CpuDesignLab.qpf
 
 
CpuDesign_nativelink_simulation.rpt
CpuDesign_nativelink_simulation.rpt
 
 
MDMux.bsf
MDMux.bsf
 
 
MDMux.v
MDMux.v
 
 
MDR.v
MDR.v
 
 
README.txt
README.txt
 
 
Registers.bdf
Registers.bdf
 
 
Registers.bsf
Registers.bsf
 
 
Registers_tb.v
Registers_tb.v
 
 
alu_mux.v
alu_mux.v
 
 
alu_mux.v.bak
alu_mux.v.bak
 
 
encoder.bsf
encoder.bsf
 
 
encoder32-5.v
encoder32-5.v
 
 
encoder32-5.v.bak
encoder32-5.v.bak
 
 
encoder32_5.bsf
encoder32_5.bsf
 
 
lpm_add_sub0.bsf
lpm_add_sub0.bsf
 
 
lpm_add_sub0.qip
lpm_add_sub0.qip
 
 
lpm_add_sub0.v
lpm_add_sub0.v
 
 
lpm_add_sub0_bb.v
lpm_add_sub0_bb.v
 
 
mux32-1.v
mux32-1.v
 
 
mux32-1.v.bak
mux32-1.v.bak
 
 
mux32_1.bsf
mux32_1.bsf
 
 
register.bsf
register.bsf
 
 
register.v
register.v
 
 
register.v.bak
register.v.bak
 
 
register64b.v
register64b.v
 
 
register64b.v.bak
register64b.v.bak
 
 
registers_tb.v.bak
registers_tb.v.bak
 
 

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# CpuDesignLab
# Designing a simple RISC computer(Phase 1)
# Includes Quartus files for R0 to R15, PC, IR, Y, Z, MAR, HI, and LO. 
# Also incorporates BUS, MDR & ALU configurations files.
# Tyler, Joshua, Dylan

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