Fix Espressif SHA512 SW fallback endianness

[gojimmypi]

Description

Related to #7505 this update fixes Espressif SHA512 HW/SW interleaving. Specifically when a hardware hash is in progress, and a separate concurrent instance of the same SHA512 is initiated. The second instance needs to fall back to software. On the Xtensa architecture, this means changing the endianness. In the RISC-V, it does not.

Note that some chipsets support hardware interleaving. That feature is not implemented yet. This PR only affects mixed hardware and software interleaving.

This PR properly first checks the HW/SW mode and then performs the SHA transformation.

Missing, is apparently a proper SHA512 interleaving test, similar to the one implemented for SHA256. Although both are implemented in test.c. and thought to be previously detecting this interleave issue; The SHA256 works properly, but the SHA512 test fails to find the problem.

I had previously fixed this problem, but the change did not make it into #7505. The problem was hidden as the respective user_settings.h for the affected platforms was missing the WOLFCRYPT_HAVE_SRP setting. That's also corrected in this PR.

Finally, there's a slight polish in the sha copy for NO_WOLFSSL_ESP32_CRYPT_HASH_SHA512 and NO_WOLFSSL_ESP32_CRYPT_HASH_SHA384.

Fixes zd# n/a

Testing

How did you test?

Tested only on Espressif using my 9-device jig.

Checklist

• added tests
• updated/added doxygen
• updated appropriate READMEs
• Updated manual and documentation