Fix: Simplify LT bus packing to 2 elements per operand#240
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diegokingston
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Jan 26, 2026
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If I'm understanding this correctly; you're essentially casting a HHW to a WL? Which will probably introduce unsoundness on the LT side, because the range-check assumptions (LT-A1/LT-A2) no longer necessarily hold if they're not enforced by the logup. |
RobinJadoul
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Jan 27, 2026
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Formally marking it as "request changes" to prevent accidental merging
RobinJadoul
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RobinJadoul
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I don't know enough about the rest of the code, but this specific unsoundness should now be addressed 👍
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Summary
Change LT bus receiver from 3× Direct packing to
Packing::DWordHHW(2 elements)Change CPU LT sender from 3 linear combinations to
Packing::DWordBL(2 elements)Both produce the same
[lo32, hi32]fingerprint, enabling interoperability with DWordWL sendersAdd constraints so everything is properly range checked
Motivation
This change enables MEMW timestamps (DWordWL format) to send to the LT bus using
Packing::DWordWL, which also produces[lo32, hi32]. Previously, LT expected 3 elements per operand which was incompatible.Changes
prover/src/tables/lt.rs: UsePacking::DWordHHWfor lhs/rhs (reads 3 columns, produces 2 bus elements)prover/src/tables/cpu.rs: UsePacking::DWordBLfor arg1/arg2 (reads 8 bytes, produces 2 bus elements)