RISCV-CPU

A RISCV CPU with 5-stage pipeline.

Test performance (Icahe Version on FPGA)

Name		Name	Last commit message	Last commit date
Latest commit History 53 Commits
Bitstream		Bitstream
Submit FPGA version		Submit FPGA version
Testdata		Testdata
.gitignore		.gitignore
Basys-3-Master.xdc		Basys-3-Master.xdc
README.md		README.md
block_ram.v		block_ram.v
cache.v		cache.v
cpu.v		cpu.v
dcache.v		dcache.v
defines.v		defines.v
document.md		document.md
ex.v		ex.v
ex_mem.v		ex_mem.v
fifo.v		fifo.v
hci.v		hci.v
id.v		id.v
id_ex.v		id_ex.v
if.v		if.v
if_id.v		if_id.v
mem.v		mem.v
mem_control.v		mem_control.v
mem_wb.v		mem_wb.v
pc_reg.v		pc_reg.v
pred.v		pred.v
ram.v		ram.v
regfile.v		regfile.v
riscv_top.v		riscv_top.v
stall_control.v		stall_control.v
testbench.v		testbench.v
uart.v		uart.v
uart_baud_clk.v		uart_baud_clk.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v